Multi-bit sigma-delta modulator employing dynamic element...

Details Multi-bit sigma-delta modulator employing dynamic element... Multi-bit sigma-delta modulator employing dynamic element...

2002-09-27

2003-08-26

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C375S252000

Reexamination Certificate

active

06611221

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multi-bit sigma-delta analog-to-digital converter and, more particularly, to a multi-bit sigma-delta analog-to-digital converter having an adaptively randomizable data weighted averaging algorithm dynamic element matching logic block.
BACKGROUND OF THE INVENTION
Conversion of analog signals to digital signals and vice versa interfaces real world systems with digital systems that read, store, interpret, manipulate and otherwise process the discrete values of sampled analog signals, many of which vary. Real world applications that convert digital signals to analog waveforms at a high resolution include systems such as, digital audio systems such as compact disc players, digital video players, and various other high performance audio applications.
Sigma-delta modulators (SDMs) have come into widespread use as a processing solution regarding these real world digital audio applications to provide a high resolution data conversion solution using low resolution building blocks. A low resolution building block, such as the single-bit DAC, provides perfect linearity which the single-bit SDM relies upon to achieve high resolution. In addition, the single-bit SDM has low sensitivity to analog component matching and large over-sampling ratios (OSRs), making it the preferred architecture for the past decade. These large OSRs arise from the inherent linearity of the single-bit DAC and the extremely small input bandwidth. To obtain higher resolution or wider bandwidth, however, higher order loops are required. Higher order loops, however, cause instability problems, resulting in reduced input range.
Multi-bit, multi-stage SDMs (MASH) relax the instability problem and require lower oversampling ratios (OSRs). The MASH architecture can provide a signal to quantization noise ratio (SQNR) greater than 16 bits even with OSRs as low as 8. The first stage of a conventional MASH architecture, as shown in
FIG. 1
, includes an n-bit ADC and an n-bit DAC in its feedback path. Generally, the ADC and DAC within the MASH architecture include discrete data elements, such as, capacitors, resistors, current sources and the like for converting electrical signals from analog to digital form and vice versa. Particularly, the DAC includes a bank of capacitors configured such that a selected number of capacitors release their electrical energy into a summing junction that produces an analog output signal equivalent to the digital input. Conversely, the ADC includes comparators combined with a voltage divider network such that each comparator compares the same reference voltage to an incrementally higher voltage level associated with the incoming analog signal. A common clock triggers the output of the comparators, such that each comparator generates a high logic (1) or a low logic (0) level with the parallel output of the comparators representing a digital “thermometer code” indicative of the incoming analog voltage level. This thermometer code may then be digitally processed to generate an n-bit digital word representing the converted analog signal.
Since some degree of variation exists among identically modeled elements due to manufacturing variations, imperfections in materials used, change in temperature, humidity, degradation, etc., noise results. In particular, any mismatch in the unit elements of the DAC causes non-linearity in the feedback path, which manifests itself as distortion as well as noise at the output. Thus, the major disadvantage of the MASH architecture is that the multi-bit DAC in the feedback path does not possess the inherent linearity of the single-bit DAC and, thus, produces distortion in the signal path.
Though component mismatches down to 0.1% can be achieved with known technologies, this is not sufficient to achieve specifications above 100 dB spurious free dynamic range (SFDR). The problem is more severe for high speed modulators having low OSRs.
FIGS. 2
a
and
2
b
illustrate the frequency spectrum at the output of a typical 2-1-1 multistage SDM having a 3-bit DAC in the first stage, where the input bandwidth is 2.5 MHz and the OSR is eight.
FIG. 2
a
displays the modulator output where the unit elements have a mismatch of 0% and
FIG. 2
b
displays the modulator output where the unit elements have a mismatch of 0.1%. As implied by
FIG. 2
b,
even a small mismatch in the unit elements can increase the noise floor and the tones substantially, thereby reducing both the signal-to-noise ratio plus distortion (SNRD) and SFDR, substantially.
There are several approaches to correct the effects of unit element mismatch. The first approach incorporates trimming the unit elements to cancel the noise at the output. Trimming, however, is expensive and hence is not suited for a low cost semiconductor environment. Another approach incorporates calibration or error correction associated with all unit elements within the SDM. This second approach, however, is very complex to implement and attempts towards commercial use have not been successful to date. The last known approach implements shaping the spectrum of DAC mismatch through the use of dynamic element matching (DEM) algorithms which algorithmically manipulate the selection of the data converter unit elements to provide a noise shaping of the mismatch errors associated with these elements.
Various DEM algorithms have been proposed to date to either randomize or shape the errors caused by the unit elements within the multi-bit DAC. Known available DEM algorithms have significant disadvantages in terms of performance as well as complexity. The most widely used DEM algorithm, data-weighted averaging (DWA), provides a good attenuation of DAC noise by ideally achieving a first-order noise shaping. Assuming the 3-bit DAC is implemented using 8 unit element capacitors, the operation of the DWA algorithm can be explained using
FIGS. 3
a,
3
b
and
3
c.
As shown, an input sequence of 2, 4, and 6 provides the starting points of the selected unit elements: A, G and C; wherein, the starting point is incremented based upon the input sequence. This ensures maximum usage of each unit element in an effort to average out each individual error associated with each unit element and, thus, provide a first order shaping of the noise associated with the multi-bit DAC. In this manner, the unit elements of the data converter may equally participate in the conversion process, thereby minimizing the effects of mismatched elements in a data converter by distributing errors due to mismatched elements.
Since the pointer increment is dependent upon input data, the DWA algorithm is dependent upon the amplitude and frequency of the input signal. As such, the conventional DWA algorithm produces in-band tones for smaller input amplitudes, which reduces the SFDR drastically as is shown by comparison of the in-band spectrum representations of the SDM output as shown in
FIGS. 4
a
and
4
b,
wherein the input signals are −4 dB and −25 dB, respectively. As shown, the amplitude and location of the in-band tones depends upon the input signal amplitude. Some of the tones appear as harmonics, thereby, reducing total harmonic distortion (THD) as well.
Furthermore, the DWA algorithm can cause folding of DAC out-of-band tones into the baseband which results in the reduction of SDM performance, reducing the SFDR drastically, particularly in modulators having a reduced over-sampling ratio. These tones, depending upon the input signal amplitude, move around within the input bandwidth. Many versions of DWA have been proposed in an attempt to eliminate these in-band tones resulting from the DWA algorithm. In a first approach, DWA aliasing tones in a multi-bit SDM can be broken up and randomized by adding dither, at the cost of increasing baseband noise, reducing dynamic range, and possibly destabilizing the modulator.
U.S. Pat. No. 6,218,977, incorporated herein by reference, discloses a method and apparatus for distributing mismatched error associated with data converter elements using a rotator circuit. The rotat

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