Multi-bit sigma-delta analog-to-digital converter with reduced s

Details Multi-bit sigma-delta analog-to-digital converter with reduced s Multi-bit sigma-delta analog-to-digital converter with reduced s

1992-03-02

1994-07-12

Williams, Howard L.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

H03M 304

Patent

active

053292820

ABSTRACT:
A multi-bit sigma-delta analog-to-digital converter (ADC) (40) includes a sigma-delta modulator (41) with a multi-bit quantizer (46) and a digital-to-analog converter (DAC) (47). An output of the DAC (47) provides an error signal of the modulator (41). The quantizer (46) provides a quantized signal having multiple bits ordered from a most-significant bit, to a second most significant bit, to at least one lower-order bit including a least-significant bit. At least two of these bits, including the most significant bit and one of the lower-order bit or bits, are provided as inputs to the DAC (47). The remaining bits are provided as inputs to a prefilter (49), which performs the same transfer function as a comparable multi-bit modulator. A summing device (49) subtracts the output of the prefilter (48) from the quantized signal. A decimation filter (50) resamples the output of the summing device (49) to provide the output of the ADC (40).

REFERENCES:
patent: 4990914 (1991-02-01), Giancarlo
patent: 5030952 (1991-07-01), Ledzius et al.
patent: 5057840 (1991-10-01), Ledzius et al.
patent: 5084702 (1992-01-01), Ribner
patent: 5134402 (1992-07-01), Miyoshi
patent: 5162799 (1992-10-01), Tanimoto
"The Design of Sigma-Delta Modulation Analog-to-Digital Converters," by Boster et al. in IEEE Journal of Solid State Circuits, vol. 23, No. 6, Dec. 1988, pp. 1298-1308.
"An Improved Sigma-Delta Modulator Architecture," by Leslie, T. and Singh, B. in IEEE ISCAS, 1990, pp. 372-375.
Cataltepe, et al. "Digitally Corrected Multi-Bit .epsilon..DELTA.Data Converters," IEEE Proc. ISCAS 1989 pp. 647-650, May 1989.

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