Multi-bit PROM memory cell

Details Multi-bit PROM memory cell Multi-bit PROM memory cell

2003-04-24

2004-02-10

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read only systems

C365S096000, C365S100000, C365S105000

Reexamination Certificate

active

06690597

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor digital memories, and more specifically to memory cell structures that permit more than one binary bit to be stored and accessed.
BACKGROUND OF THE INVENTION
Semiconductor digital memories typically comprise arrays of memory cells that store one binary bit capable of two states, e.g., “1” or “0”. Fuse and antifuse memory bit cells represent the binary states of “1” and “0” by the condition of the fuse, e.g., open =1, and closed =0, or vice versa. A diode is usually included at each fuse location to make each bit in an array readable one at a time using bit and word address lines. Such diodes are reverse-biased if the row and column of the bit are not being addressed, and forward-biased if they are being addressed.
An antifuse is the opposite of a regular fuse, an antifuse is normally an open circuit until a programming current, e.g., about five milliamperes, is forced through it. Poly-diffusion antifuses, e.g., use heat generated by high current densities to melt a thin insulating dielectric layer between electrodes. The programming current drives dopant atoms from the polysilicon and diffusion electrodes into a resistive silicon link about twenty nanometers in diameter results. Actel refers to its antifuse technology as programmable low-impedance circuit element (PLICE).
A typical poly-diffusion antifuse oxide-nitride-oxide (ONO) dielectric sandwich comprises silicon dioxide (SiO
2
) grown over an n-type antifuse diffusion, a silicon nitride (Si
3
N
4
) layer, and another thin silicon dioxide (SiO
2
) layer. An antifuse such as this with a layered ONO-dielectric structure has narrower range of blown antifuse resistance values, as compared to a single-oxide dielectric. The effective electrical thickness the layered ONO-dielectric structure is equivalent to ten nanometers of SiO
2
The Si
3
N
4
has a higher dielectric constant than SiO
2
, so the actual thickness can be less than ten nanometers.
The average resistance of a blown antifuse depends on the fabrication process and the programming current used. In one particular technology, a programming current of five milliamperes may result in an average blown antifuse resistance of about 500-ohms. The correct level of switch current depends on the device size and the top meal used. Increasing the programming current to fifteen milliamperes typically reduces the average antifuse resistance, e.g., to 100-ohms. Conducting filaments of metal are assumed to be the principle vehicle for current flow after programming the switch. The typical on-to-off resistance ratio is on the order of 1:100,000.
Once an antifuse is programmed, the process cannot be reversed. An Actel 1010, for example, contains about 112,000 antifuses, but only two percent of the fuses are ever programmed in a typical application.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory cell structure for increased bit storage densities.
Briefly, a memory cell embodiment of the present invention comprises at least two antifuses in series with a diode. Each antifuse expresses a different resistance from the others when blown, and each requires an escalating programming voltage or current over the last to be programmed. The antifuse structures differ in their respective geometries and materials so that a low programming voltage will blow the more sensitive fuse first, and a higher voltages will program the lesser sensitive fuses thereafter.
An advantage of the present invention is that a memory device is provided that has a high bit density.
Another advantage of the present invention is that a memory device is provided that can be expanded vertically in additional layers.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment as illustrated in the drawing figures.


REFERENCES:
patent: 5200652 (1993-04-01), Lee
patent: 5412593 (1995-05-01), Magel et al.

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