Multi-bit per stage pipelined analog to digital converters

Details Multi-bit per stage pipelined analog to digital converters Multi-bit per stage pipelined analog to digital converters

2008-02-05

2009-08-11

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

07573417

ABSTRACT:
Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches.

REFERENCES:
patent: 6784824 (2004-08-01), Quinn
patent: 6956519 (2005-10-01), Huang
patent: 7002504 (2006-02-01), McMahill
patent: 7209068 (2007-04-01), Chen et al.
patent: 7471228 (2008-12-01), Cho
patent: 2006/0071709 (2006-04-01), Maloberti et al.
Brandt et al., “A 75-mW, 10-b, 10 MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist”, IEEE J. Solid State Circuits, vol. 34, No. 12, pp. 1788-1795, Dec. 1999.
Daito et al., “A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration,” IEEE J. Solid-State Circuits, vol. 41, No. 11, pp. 2417-2423, Nov. 2006.
Gupta et al., “A 1GS/s 11b Time Interleaved ADC in 0.13um CMOS”, ISSCC Dig. Tech. Papers, pp. 576-577, Feb. 2006.
Kim et al., “A 10-b, 10MS/s CMOS A/D Converter”, IEEE J. Solid State Circuits, vol. 32, No. 3, pp. 302-311, Mar. 1997.
Mehr et al., “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, No. 3, pp. 302-311, Mar. 2000.
Nagaraj et al., “A 250 mW 8-b, 52 Msamples/s Parallel-pipelined A/D Converter with Reduced Number of Amplifiers”, IEEE J. Solid State Circuits, vol. 32,pp. 312-320, Mar. 1997.
Singer et al., “A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter,” in symp. VLSI Circuits Dig. Tech. Papers, Jun. 1996, pp. 38-39.
U.S. Appl. No. 12/024,893, filed Feb. 1, 2008, Bailey.
U.S. Appl. No. 12/024,909, filed Feb. 1, 2008, Bailey.
U.S. Appl. No. 12/025,897, filed Nov. 20, 2007, Bailey et al.

Affiliated with

Also associated with

Rating

Multi-bit per stage pipelined analog to digital converters does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-bit per stage pipelined analog to digital converters, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-bit per stage pipelined analog to digital converters will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4086124