Multi-bit-per-cell read only memory circuit

Details Multi-bit-per-cell read only memory circuit Multi-bit-per-cell read only memory circuit

1983-07-01

1986-04-29

Moffitt, James W.

Static information storage and retrieval

Read only systems

Semiconductive

365184, G11C 700, G11C 1140

Patent

active

045861633

ABSTRACT:
A data memory circuit is provided including a plurality of depletion type MOS transistors connected in series, each of which stores data including two bits in the form of a threshold voltage. One end of the memory circuit is kept at a power source level and the second terminal thereof is kept at a ground potential level. 0 V is applied to the gate electrode of one selected MOS transistor while the power source voltage is applied to the gate electrodes of the remaining MOS transistors. As a result, a voltage equal to an absolute value of the threshold voltage of the selected MOS transistor is produced at the second terminal. A converter converts the voltage produced at the second terminal into corresponding binary coded data.

REFERENCES:
patent: 4107548 (1978-08-01), Sakaba et al.
patent: 4202044 (1980-05-01), Beilstein et al.
Patent Abstracts of Japan, vol. 6, No. 18, Feb. 2, 1982.
Kawagoe et al., "Minimum Size ROM Structure Compatible with Silicon-Gate E/D MOS LSI," IEEE Journal of Solid-State Circuits, vol., SC-11, No. 3, Jun. 1976.

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