Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2007-01-30
2007-01-30
Lam, David (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185240
Reexamination Certificate
active
11101938
ABSTRACT:
A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.
REFERENCES:
patent: 4139911 (1979-02-01), Sciulli et al.
patent: 4218764 (1980-08-01), Furuta et al.
patent: 4253059 (1981-02-01), Bell et al.
patent: 4460982 (1984-07-01), Gee et al.
patent: 4612630 (1986-09-01), Rosier
patent: 4694454 (1987-09-01), Matsuura
patent: 4703196 (1987-10-01), Arakawa
patent: 4703453 (1987-10-01), Shinoda et al.
patent: 4733394 (1988-03-01), Giebel
patent: 4763305 (1988-08-01), Kuo
patent: 4779272 (1988-10-01), Kohda et al.
patent: 4799195 (1989-01-01), Iwahashi et al.
patent: 4809231 (1989-02-01), Shannon et al.
patent: 4827450 (1989-05-01), Kowalski
patent: 4937787 (1990-06-01), Kobatake
patent: 4962322 (1990-10-01), Chapman
patent: 4964079 (1990-10-01), Devin
patent: 5065364 (1991-11-01), Atwood et al.
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5119330 (1992-06-01), Tanagawa
patent: 5122985 (1992-06-01), Santin
patent: 5132935 (1992-07-01), Ashmore, Jr.
patent: 5151906 (1992-09-01), Sawada
patent: 5157629 (1992-10-01), Sato et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5200922 (1993-04-01), Rao
patent: 5200959 (1993-04-01), Gross et al.
patent: 5239505 (1993-08-01), Fazio et al.
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 5263032 (1993-11-01), Porter et al.
patent: 5270551 (1993-12-01), Kamimura et al.
patent: 5270979 (1993-12-01), Harari et al.
patent: 5278794 (1994-01-01), Tanaka et al.
patent: 5313427 (1994-05-01), Schreck et al.
patent: 5321655 (1994-06-01), Iwahashi et al.
patent: 5327383 (1994-07-01), Merchant et al.
patent: 5335198 (1994-08-01), Van Buskirk et al.
patent: 5341334 (1994-08-01), Maruyama
patent: 5347489 (1994-09-01), Mechant et al.
patent: 5365486 (1994-11-01), Schreck
patent: 5377147 (1994-12-01), Merchant et al.
patent: 5394359 (1995-02-01), Kowalski
patent: 5450363 (1995-09-01), Christopherson et al.
patent: 5465236 (1995-11-01), Naruke
patent: 5523972 (1996-06-01), Rashid et al.
patent: 5532962 (1996-07-01), Auclair et al.
patent: 5583812 (1996-12-01), Harari
patent: 5648934 (1997-07-01), O'Toole
patent: 5652720 (1997-07-01), Aulas et al.
patent: 5657332 (1997-08-01), Auclair et al.
patent: 5675537 (1997-10-01), Bill et al.
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5703506 (1997-12-01), Shook et al.
patent: 5712815 (1998-01-01), Bill et al.
patent: 5717632 (1998-02-01), Richart et al.
patent: 5751639 (1998-05-01), Ohsawa
patent: 5761125 (1998-06-01), Himeno
patent: 5835413 (1998-11-01), Hurter et al.
patent: 5889698 (1999-03-01), Miwa et al.
patent: 5905673 (1999-05-01), Khan
patent: 5909449 (1999-06-01), So et al.
patent: 6151246 (2000-11-01), So et al.
patent: 6199139 (2001-03-01), Katayama et al.
patent: 97460009.0 (1997-08-01), None
patent: WO 9012400 (1999-10-01), None
Lee et al., “Error Correction Technique for Multivalued MOS Memory,”Electronic Letters, vol. 27, No. 15, Jul. 18, 1991, pp. 1321-1323.
Communication Pursuant to Article 96(2) EPC for SanDisk Corporation dated Aug. 8, 2005, 5 pages.
Communication Pursuant to Article 96(2) EPC for Application No. 98 307 184.6 for SanDisk Corporation, Aug. 7, 2006, 3 pages.
So Hock C.
Wong Sau C.
Lam David
Parsons Hsue & de Runtz LLP
SanDisk Corporation
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