Multi-bit-per-cell flash EEPROM memory with refresh

Details Multi-bit-per-cell flash EEPROM memory with refresh Multi-bit-per-cell flash EEPROM memory with refresh

2005-05-24

2005-05-24

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185240, C365S185250

Reexamination Certificate

active

06898117

ABSTRACT:
A memory architecture for a non-volatile analog or multiple-bits-per-cell memory includes multiple separate memory arrays and multiple read/write pipelines. The multiple read/write pipelines share a read circuit and/or a write circuit to reduce the circuit area of each pipeline and the circuit area of the memory as a whole. In one embodiment, a shared write circuit generates a programming voltage that changes with an input signal representing values to be written to the memory. Each pipeline includes a sample-and-hold circuit that samples the programming voltage when the pipeline begins a write operation. The write circuit can additionally generate a verify voltage that a second sample-and-hold circuit in each pipeline samples when starting a write operation.

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