Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2000-10-06
2001-10-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185090, C365S185220, C365S185240, 37
Reexamination Certificate
active
06307776
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to non-volatile semiconductor memory and more specifically to circuits and methods for detecting and correcting data errors in a memory storing multiple bits per memory cell.
2. Description of Related Art
Conventional electrically erasable non-volatile semiconductor memories such as E
2
PROMs and flash memories have memory cells that include transistors with programmable threshold voltages. For example, a floating gate transistor or a split gate transistor has a threshold voltage that is programmed or erased by charging or discharging a floating gate located between a control gate and a channel in the transistor. The amount of charge on the floating gate of the transistor determines the voltage that must be applied to the control gate to cause charge carrier inversion in the underlying channel and therefore determines the threshold voltage of the transistor. Data is written in such memory cells by charging or discharging the floating gates of the memory cells to achieve threshold voltages corresponding to the data.
A binary memory stores one bit of data per memory cell. Accordingly, floating gate transistors in binary memory cells have two distinguishable states, a high threshold voltage state and a low threshold voltage state. Any memory cell having a threshold voltage above a cut-off threshold voltage value is in the high threshold voltage state and stores a bit value, 1 or 0, that corresponds to the high threshold state. Memory cells having threshold voltages below the cut-off are in the low threshold voltage state and store the bit value, 0 or 1, corresponding to the low threshold voltage state.
A multibit-per-cell memory stores multiple bits per memory cell. Accordingly, a range of threshold voltages for a memory cell is divided into a number of states corresponding to the possible multibit data values stored in the memory cell. For example, a memory that stores two bits of data per memory cell has a range of suitable threshold voltages for memory cells that is divided into four states. A first state includes threshold voltages below a first cut-off. A second state includes threshold voltages between the first cut-off and a second cut-off. A third state includes threshold voltages between the second cut-off and a third cut-off, and a fourth state includes threshold voltages above the third cut-off.
A concern in non-volatile semiconductor memory is drift or unintended changes in the threshold voltages of memory cells. For example, over time, charge tends to leak from the floating gates of memory cells and change the threshold voltages of the cells. Charge leakage decreases the threshold voltage of an N-channel memory cell. Alternatively, a floating gate or an insulator surrounding the floating gate can collect or trap charge and increase the threshold voltage of a cell. Further, operation of the memory, for example, programming or reading stresses memory cells not being accessed and can change threshold voltages. Changes in the threshold voltage are a problem because the state of the memory cell and the data value stored in the memory cell can change and create a data error. Such data errors are intolerable in many memory applications. The problem is worse for multibit-per-cell memories than for binary memories because the range of threshold voltages corresponding to a particular state is typically smaller in a multibit-per-cell memory which makes changes in the state of the memory cell more likely.
Multibit-per-cell memories that are resistant to data errors are sought.
SUMMARY
In accordance with the invention, a range of possible threshold voltages for a memory cell in a multibit-per-cell memory is divided into allowed states associated with data values and forbidden zones between the allowed states. A memory cell being written is programmed into an allowed state. Subsequent reading of the memory cell indicating that the threshold voltage of the memory cell is in a forbidden zone indicates that the threshold voltage of the memory cell has changed and is in error. A memory cell with a threshold voltage in a forbidden zone can be flagged as a data error or corrected by increasing or decreasing the threshold voltage to an adjacent allowed state. One specific embodiment of the invention is a flash memory that presumes charge loss in the memory cells and programs the threshold voltage of a memory cell up to the next allowed state when the memory detects that the threshold voltage of the memory cell is in a forbidden zone. Alternatively, data errors can be corrected by reading the data values from a sector of memory cells including one or more memory cells containing one or more errors, erasing the sector, and then programming the sector with corrected data values.
In accordance with another aspect of the invention, a non-volatile memory performs a refresh cycle in which memory cells are read and threshold voltages of the memory cells are reprogrammed to an allowed state. In a flash EPROM, the refresh cycle can refresh data in a single sector or an entire memory array. In alternative embodiments, the refresh cycle is triggered by external circuit attached to a monolithic integrated circuit memory or is self-triggered in the memory. Refreshes may be performed at periodic intervals of operation, as part of a power-up procedure for the memory, or transparently during each read operation performed by the memory.
According to a further aspect of the invention, adjacent states (i.e., ranges of threshold voltages) for a multibit-per-cell memory cell are mapped to data values using gray coding or another coding system instead of a direct monotonic mapping from threshold voltages to data values. With such coding, a drift from one threshold voltage state to an adjacent threshold voltage state causes only a single bit error. Such single bit errors can be detected and corrected using error correction codes. The gray coding of allowed states can be used with or without forbidden zones between the coded states and/or refresh cycles to correct stored data.
One specific embodiment of the invention is a non-volatile semiconductor memory that includes: an array of memory cells where each memory cell that stores data has a threshold voltage that identifies a multibit data value; an error detection circuit; and a control circuit that controls refresh operations. The error detection circuit detects errors in threshold voltages of memory cells storing data and in response to detecting an error, signals that a memory cell or a memory sector requires a refresh operation. The refresh operation can occur immediately, periodically, during the next start up of the memory, or when the memory becomes inactive for a period of time. During the refresh operation, the control circuit writes a corrected threshold voltage that corrects the error that the error detection circuit detected. The corrected threshold voltage can be written to the original memory cell containing the error or another memory cell that replaces the original memory cell after the refresh operation. The control circuit can read refresh information or an erase count for a sector containing the memory cell having the error and based on the information read select where to write the corrected threshold voltage.
The error detection circuit can detect the error by finding a threshold voltage in a zone forbidden to threshold voltages corresponding to data or from an error detection code stored when the threshold voltage was written. Gray coded allowed threshold voltage states are preferred so that a shift in threshold voltage from one allowed state to a neighboring allowed state causes only a single bit error in the data stored in the memory cell. The memory can further include a data correction circuit that processes an error correction code to identify the corrected threshold voltage to correct the detected error.
Another specific embodiment of the invention is a non-volatile semiconductor memory including an array of memory cells and a reference voltage generator. In the array, each
So Hock C.
Wong Sau C.
Lam David
Nelms David
SanDisk Corporation
Skjerven Morrill & MacPherson LLP
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