Multi-bit-per-cell flash EEPROM memory with refresh

Details Multi-bit-per-cell flash EEPROM memory with refresh Multi-bit-per-cell flash EEPROM memory with refresh

1998-11-25

2000-11-21

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518524, 371 214, G11C 1606

Patent

active

06151246&

ABSTRACT:
A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.

REFERENCES:
patent: 4964079 (1990-10-01), Devin
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5751639 (1998-05-01), Ohsawa
patent: 5761125 (1998-06-01), Himeno
patent: 5909449 (1999-06-01), So et al.

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