Multi-bit error scattering arrangement to provide fault tolerant

Details Multi-bit error scattering arrangement to provide fault tolerant Multi-bit error scattering arrangement to provide fault tolerant

1982-06-16

1984-12-11

Atkinson, Charles E.

Excavating

365200, 391 2, 391 38, G06F 1110

Patent

active

044882980

ABSTRACT:
A fault alignment exclusion method and apparatus is disclosed which operates to prevent the alignment of two or more defective bit storage locations at an address in a memory array. The disclosed memory comprises a plurality (n.times.m) of separate memory chips arranged in a matrix of n rows and m columns. Each of the chips contains a large plurality (64K) of individually addressable bit locations. A plurality of data words, each containing m (72) bit positions are transferred from the memory array to a n (16) word m (72) bit position buffer during a memory read operation. Steering logic responsive to control signals is disposed between the memory and the buffer which permits the n chips in each column of the array to be effectively rearranged selectively within the respective columns so that the relationship of any given chip to a position of the 16 storage positions in a corresponding buffer column may be selectively changed by the control signals applied to the steering logic. The control signals are developed based on defect data stored in an error map such that each memory address contains no more than one defective location.

REFERENCES:
patent: 3644902 (1972-02-01), Beausoleil
patent: 3781826 (1973-12-01), Beausoleil
patent: 3897626 (1975-08-01), Beausoleil
patent: 4074236 (1978-02-01), Ishida
patent: 4365318 (1982-12-01), Aichelmann, Jr. et al.
P. M. Ryan, Fault Realignment Through Grouping of Compatible Faulty Memory Chips, IBM Tech. Discl. Bulletin, vol. 26, No. 6, Nov. 1983, pp. 2753-2754.
Beausoleil, Maintenance for Memory with Error Correction, IBM Technical Disclosure Bulletin, vol. 11, No. 12, May 1969, pp. 1692-1693.
C. L. Chin, Fault Dispersion in Computer Memories, IBM Technical Disclosure Bulletin, vol. 25, No. 11A, Apr. 1983, pp. 5836-5838.

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