Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Including structure for detecting or indicating overflow...
Reexamination Certificate
2001-02-15
2003-04-29
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Including structure for detecting or indicating overflow...
C377S026000, C377S107000
Reexamination Certificate
active
06556645
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a multi-bit counter, and, more particularly, to a multi-bit counter capable of executing high speed operation by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by a clock signal.
FIG. 1
is a block diagram of a typical multi-bit counter, e.g., 6-bit counter. As shown in
FIG. 1
, the 6-bit counter comprises unit counters CNT
1
to CNT
6
for detecting an initial input value applied via external address signals EADD<0:5>. The external input can be set by a count set signal CNTSET, and a count increase signal CNTINC increments the count in combination with a carry CAi to output internal address signal IADD<0:5>, and first to fourth carry generators
1
-
4
, each for combining the carry CAi and the internal address signal IADDi of the corresponding unit counter, for applying the combined signal to the carry CA(i+1) of the next unit counter.
Each of the carry generators
1
-
4
includes a NAND gate ND for NAND-operating the carry CA(i−1) of the previous unit counter CNT(i−1) and the internal address signal IADD(i−1) of the previous unit counter CNT(i−1), and an inverter INV for inverting the output of the NAND gate ND to output the carry CAi. Here, because a carry input port of the first unit counter CNT
1
is coupled to a power voltage, the internal address signal IADD
0
of the first unit counter is directly applied to the carry CA
1
of the second unit counter CNT
2
.
The unit counter CNTi as shown in
FIG. 2
, includes a NAND gate ND
1
for NAND-operating the carry CA(i−1) of the previous unit counter CNT(i−1) and the counter increase signal CNTINC to output an inverted increase control signal /INC; a first inverter INV
1
for inverting the output of the NAND gate ND
1
to an increase control signal INC; a second inverter INV
2
for inverting the count set signal CNTSET; a third inverter INV
3
for inverting the external address signal EADDi; a first transfer gate TG
1
for selectively transferring the output of the third inverter INV
3
under control of the count set signal CNTSET and the inverted count set signal /CNTSET; fourth and fifth inverters INV
4
, INV
5
, the input of the fourth inverter coupled to the output of the fifth inverter and the input of the fifth inverter coupled to the output of the fourth inverter latching the signal selectively transferred through a first transfer gate TG
1
; a sixth inverter INV
6
for inverting the output signal of the fourth inverter INV
4
; seventh and eighth inverters INV
7
, INV
8
, the input of the seventh inverter coupled to the output of the eighth inverter and the input of the eighth inverter coupled to the output of the seventh inverter for latching the output signal of the sixth inverter INV
6
; and a second transfer gate TG
2
for selectively transferring the signal transferred selectively through the first transfer gate TG
1
under control of the increase control signal INC and the inverted increase control signal /ICN, wherein the output signal of the seventh inverter INV
7
and the signal selectively transferred through the second transfer gate TG
2
are coupled to generate the internal address signal IADDi.
Increase control signal INC is applied to the power ports of the fifth and sixth inverters INV
5
, INV
6
and inverted increase control signal /INC is applied to the ground ports of the fifth and sixth inverters INV
5
, INV
6
. In addition, inverted increase control signal /INC is applied to the power port of eighth inverter INV
8
and increase control signal INC is applied to the ground port of eighth inverter IVN
8
.
The conventional multi-bit counter as described above outputs an internal address signal and sets the internal state of each counter to prepare for generating the next internal address signal as directed by a clock signal. However, as the frequency of the clock signal increases, the margin of time required to compare and properly increase the output of each bit counter in the multi-bit counter becomes insufficient, and the frequency of the clock signal that can be used for the conventional multi-bit counter is restricted.
SUMMARY OF THE INVENTION
One aspect of the present invention provides a multi-bit counter capable of high-speed operation by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by using a clock signal.
In accordance with an aspect of the present invention, there is provided a multi-bit counter comprising a multiplicity of unit counters, each for receiving bit combinations of a unit external address signal, setting an external input by a count set signal and increasing bits by a count increase signal and a carry to output an internal address signal and a final state signal; and a plurality of logically combining means, each for combining the carry and the final state signal of each unit counter, for applying the combined signal to the carry of the next unit counter, the unit counter including: a NAND gate for NAND-operating the count increase signal and a carry to output an increase control signal; a first inverter for inverting the output of the NAND gate to output an increase control signal; a multiplicity of state controlling units, each receiving the bit combinations of the unit external address signal to output a number of state signals; a multiplicity of state units for presetting possible states for the bit combinations of the unit external address signal by using the number of state signals from the multiplicity of state controlling units to selectively output the bit combinations as a plurality of internal address signals; and second to fifth inverters, the input of the second inverter coupled to the output of the third inverter and the input of the third inverter coupled to the output of the second inverter, the input of the fourth inverter coupled to the output of the fifth inverter and the input of the fifth inverter coupled to the output of the fourth inverter, for latching the plurality of internal address signals selectively output by the number of state units.
REFERENCES:
patent: 5561674 (1996-10-01), Cho
patent: 6314155 (2001-11-01), Shona et al.
Hynix / Semiconductor Inc.
Townsend and Townsend / and Crew LLP
Wambach Margaret R.
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