Pulse or digital communications – Cable systems and components
Reexamination Certificate
1998-11-19
2001-08-21
Pham, Chi (Department: 2631)
Pulse or digital communications
Cable systems and components
C375S292000, C341S055000, C327S063000
Reexamination Certificate
active
06278740
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated-circuit signaling, and more particularly to encoding of differential signals.
BACKGROUND OF THE INVENTION
A wide variety of digital systems communicate using signal wires. Integrated circuits or chips contain output buffers or drivers that drive an external wire such as a metal trace on a printed-circuit board or a cable connecting networked computers. Two basic techniques are used to pass digital information over external wires: single-wire and two-wire (differential) transmission.
The most common method is to simply transmit the signal over a single external wire.
FIG. 1A
highlights single-wire transmission. Chip
10
sends a signal to chip
12
over single external wire
18
. Output driver
14
in chip
10
receives an internal signal from within chip
10
and drives a much higher current out to external wire
18
. An input buffer or receiver
16
in chip
12
is connected to external wire
18
. Receiver
16
determines the logical value of the signal on external wire
18
and amplifies and buffers the received signal to internal circuitry within chip
12
.
FIG. 1B
shows that the signal on the single wire is compared with a logic threshold. Input buffer receivers are designed to have a voltage midpoint or threshold V
T
that the input signal is compared with. The “comparison” with the threshold V
T
may be implicit in the design and technology of the input buffer rather than an explicit comparison of two voltages. Thus when the received signal is above V
T
a logical high is sensed, while a logical low is sensed when the received signal is below V
T
.
The actual voltage threshold can vary with the technology (process), power-supply voltage, and even the temperature. The ground levels of the two chips can differ. Noise can be coupled into the external wire or to the input buffer through power or ground supplies, or even from other internal circuitry. The noise can raise or lower the threshold significantly. When noise is sufficiently large or the threshold variation is extreme, the wrong logical value of the signal on the external wire can be detected. System failures can result.
The signal transmitted over the single wire may change rapidly. In higher-speed systems it may be desired to sense the signal before the transmitter has finished driving the external wire fully to the intended logic levels. Transmission through noisy environments may also be necessary.
Differential or two-wire transmission is a more robust signaling technique.
FIG. 2A
shows a differential signal passed between two chips. Rather than use a single wire for each signal, two wires
30
,
32
together carry a single logical signal. The wires carry complementary signals: when wire
30
is driven low by driver
22
, wire
32
is driven high by driver
24
. When driver
22
drives wire
30
high, driver
24
drives wire
32
low. At steady-state after drivers
22
,
24
have had enough time to charge or discharge capacitances on wires
30
,
32
, the logical states of the two wires
30
,
32
are opposite.
Inverter
25
inverts an internal signal in chip
10
so that drivers
22
,
24
always drive opposite signals to wires
30
,
32
. Receiver
26
in chip
12
receives both wires
30
,
32
, and compares their voltages. When the voltage on wire
30
is higher than the voltage on wire
32
, a logical high is detected and output to internal circuitry in chip
12
. Otherwise, a logical low is detected.
FIG. 2B
shows waveforms of a differential pair of wires. Wire
30
has waveform
30
′, while wire
32
has waveform
32
′. When
30
′ is higher in voltage than
32
′, such as at the beginning and end of
FIG. 2B
, a logical high is sensed. When
32
′ is higher than
30
′, such as in the middle, a logical low is detected.
Since the two wires
30
,
32
are usually in close proximity to one another, and of the same length, any noise injected into one wire is also injected into the other wire. Thus external noise tends to cancel out. Noise from within chip
12
, such as ground or power level variations, affects both wires
30
,
32
equally. The relative voltages of the two wires, or voltage difference, is not affected by such common-mode noise. Enormous amounts of common-mode noise can be tolerated by differential signaling. There is no fixed threshold voltage that each of the two wires is compared to, as was true for single-wire sensing. Thus threshold variations are not problematic.
The transmitter chip
10
can have a different ground potential than receiver chip
12
, since the ground shift affects both wires
30
,
32
equally. Very small voltage differences between the two wires
30
,
32
can be detected and amplified using current technology. Sensing is faster since smaller voltage swings can be used. Sometimes the voltage swings of the output drivers is purposely limited or clamped so that external capacitances are not full charged. This reduced power consumption and limits noise generated by the two wires. Radiation causing electromagnetic interference (EMI) is also reduced when voltage swings are limited.
FIG. 3
illustrates a prior-art signaling technique using differential-pairs or wires. Chip
10
transmits a multi-signal bus to chip
12
using differential pairs of wires
30
,
32
. One bit of the bus is transmitted over every two external wires
30
,
32
. Differential comparators
26
in chip
26
each receive a pair of input wires
30
,
32
, compare the two inputs, and generate a single bit that is output to internal bus
34
.
The 6 bits of internal bus
34
require 12 external wires. Each bit of internal bus
12
was transmitted as a true and a complement signal over a pair of external wires. In general, differential transmission of an N-bit bus requires 2N external wires.
While such differential signaling techniques are more noise tolerant than single-wire signaling, costs are higher. The number of external wires is doubled. Bonding pads for external wires occupy a large area on many integrated circuit chips, increasing cost. Leads on the IC packages are also limited. Increasing the number of external wires connected to a chip, or its lead count, is expensive since larger packages may be required.
What is desired is a differential signaling technique that uses fewer wires. It is desired to reduce the number of external wires needed when transmitting digital signals. It is desired to use differential-comparator receivers that are insensitive to common-mode noise. Differential sensing is desired for noise immunity, while differential transmission is desired so that voltage swings and noise generation can be limited. A compressed differential-signaling technique is desired that uses fewer wires. It is desired to use fewer than 2N external wires while still benefiting from differential sensing.
SUMMARY OF THE INVENTION
A group-differential receiver has a plurality of inputs from X external wires. The X external wires are for transmitting N bits of information, where X is less than 2N but greater than N.
A plurality of differential comparators are for comparing each of the X external wires to a remaining X−1 other wires in the X external wires. Each differential comparator generates a compare output for a pair of wires. A plurality of X majority blocks each receives X−1 compare outputs from a group of X−1 differential comparators. Each differential comparator in the group has a target wire of the X external wires as a comparator input and one of a remaining X−1 other wires as another comparator input.
Each majority block outputs a target state of the target wire as a logic state of a majority of the X−1 compare outputs received by the majority block. A decoder receives X target states from the plurality of X majority blocks, and converts the X target states to the N bits of information. Thus the N bits of information are extracted by differential-comparison and majority-detection of the X external wires.
In further aspects of the invention an inverter is coupled to
Auvinen Stuart T.
Gates Technology
Pham Chi
Phu Phuong
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