Multi-bank synchronous semiconductor memory device

Details Multi-bank synchronous semiconductor memory device Multi-bank synchronous semiconductor memory device

1997-07-25

1998-06-09

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36523008, 365233, 36518908, G11C 800, G11C 700

Patent

active

057645841

ABSTRACT:
A read register and a data transfer circuit are provided to implement two separate data transfer paths with respect to a preamplifier, for alternately transferring data through these two paths. Thus, the data can be transferred with no data collision in each clock cycle. The data are transferred at a high speed every clock cycle regardless of the bank number and the CAS latency in a multi-bank synchronous memory device.

REFERENCES:
patent: 5471430 (1995-11-01), Sawada et al.
patent: 5592434 (1997-01-01), Iwamoto et al.

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