Multi-bank synchronous memory system with cascade-type memory ce

Details Multi-bank synchronous memory system with cascade-type memory ce Multi-bank synchronous memory system with cascade-type memory ce

1995-02-17

1997-03-11

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, 365226, G11C 800

Patent

active

056108729

ABSTRACT:
A synchronous memory system with a cascade-type memory cell structure has memory cells having a cascade type construction (or NAND type configuration), a row decoder, save registers, a sense amplifier, and a selector. The selector transmits a control signal to halt a sense operation for the memory cells when the sense operation for a target memory cell to be accessed is completed. The row decoder includes a decoder for decoding a row address, a latch circuit, a word line driver. The latch circuit stores a result of a decode operation, and the word line driver comprises a PMOS transistor and a NMOS transistor connected in series. A 8 volt power (V.sub.pp) is supplied to the PMOS transistor in the word line driver.

REFERENCES:
patent: 5282171 (1994-01-01), Tokami et al.
patent: 5287312 (1994-02-01), Okamura et al.
patent: 5371697 (1994-12-01), Yamada
patent: 5463592 (1995-10-01), Ishikawa

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