Static information storage and retrieval – Interconnection arrangements – Transistors or diodes
Reexamination Certificate
2001-09-19
2004-05-18
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
Transistors or diodes
C365S063000, C365S051000, C365S230030
Reexamination Certificate
active
06738279
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of memory logic devices and more specifically to memory devices having multiple banks of memory arrays. More particularly, the present invention relates to memory arrays that allow for word-line banking and bit-line banking. Still more particularly, the present invention relates to memory array that uses a combination of word-line banking, bit-line banking and I/O multiplexing utilizing tilable components.
2. Description of the Background Art
Memory devices are well known in the semiconductor industry. Memory cores for integrated circuits continue to be improved. Because of the proliferation and popularity of Application Specific Integrated Circuits (ASIC), there is a need for improved designs for memory arrays. New memory arrays are needed because of the every decreasing size and power requirements. For example, new uses for ASICs such as cellular telephones, portable computers, and hand held devices require new memory arrays that require less circuit area to implement, and consume less power to extend battery life.
There are a number of approaches in the prior art for making ultra low power and high speed memory devices using multiple banks of memory arrays. A typical prior art multiple bank memory is shown in FIG.
1
. As can be seen, the prior art multiple bank memory includes an X-decoder
108
, control and pre-decoding logic
120
, and pairs of reference columns
102
,
114
, memory cells arrays
104
,
112
, word-line drivers
106
,
110
, pre-charge circuits and Y-decoders or multiplexers
116
,
122
, and sense amplifiers and input/output (I/O) circuits
118
,
124
. While the prior art provides some power reduction and speed improvement, there are no multiple bank prior art designs that utilize any type of tilable interconnecting structure between the multiple banks or portions of the arrays themselves. Instead, the prior art creates such multiple bank designs with either custom layouts or utilizing place and route tools to add the connectivity needed between the multiple banks of memory cells. Thus, the prior art requires a brute force approach to making multiple bank memories where there is significant design effort required each time the memory is added with other components in an ASIC.
In particular, when used in a memory compiler implementation, the conventional banking approach has a number of shortcomings. First, routing of signals in the memory is difficult and consumes circuit area, in addition to requiring place and route capability for the manufacturing process. As depicted by the lines between the sense amplifiers
118
and
124
, routing adds multiplexing, delay and area as compared with single bank architectures. Second, there is an area penalty because the multiplexer lines need to be switched between arrays. Third, the additional capacitance of the multiplexer lines degrades the performance of the device. Finally, the conventional architecture shown in
FIG. 1
provides non-optimum aspect ratios, especially when the word size increases in width. This often results in an additional area penalty and a tighter pitch with which to work.
Therefore, there is a need for systems and method for constructing multiple bank memory cell arrays that are tilable, smaller in size, consume less power, and reduce electrical interference.
SUMMARY OF THE INVENTION
The present invention overcomes the deficiencies and limitations of the prior art with a unique architecture for multiple bank memory cell arrays. The architecture for multiple bank memory cell arrays is advantageous because of a number of features. First the multiple bank memory cell of the present invention includes a novel technique for word-line banking that provides a combined array utilizing a tilable connection that does not require routing, and eliminates redundant reference columns. The word-line banking of the present invention may also be used independent of the type of memory cells forming the combined array. Second, the present invention also includes a novel technique for bit-line banking that eliminates sense amplifiers, provides for tilable connection between the sense amplifiers and the input/output circuit, and maintains an optimum aspect ratio. Finally, the present invention also includes a tilable method for providing coupling and multiplexing between input/output circuits.
A preferred embodiment of a multiple bank memory array according to the present invention includes a combined memory array, an X-decoder, a first word-line driver, a second word-line driver, a reference column, a Y-multiplexer and pre-charging circuit, a sense amplifier and input/output circuit, and control and pre-coding logic. Signals are received and applied to the combined memory array and the other components via the control and pre-decode logic and the input/output circuit. The control and pre-decode logic receives control signals to control and address the combined memory array. Data is input and output to the combined memory array via the input/output circuit. The combined array is particularly advantageous because it reduces the power consumed by activating only half the word line at a given time. In other words, half the word line is switching and half the bit lines are pre-charging and discharging. The combined array is also advantageous in that routing is not required for the multiple banks because the arrays are merged into a single array that is partitioned using the most significant bit of the X address value.
These and other features and advantages of the present invention may be better understood by considering the following detailed description of a preferred embodiment of the invention. In the course of this description, reference will frequently be made to the attached drawings.
REFERENCES:
patent: 6002607 (1999-12-01), Dvir
patent: 6185121 (2001-02-01), O'Neill
Fenwick & West LLP
Tran Andrew Q.
Virage Logic Corporation
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