Multi-bank memory with word-line banking

Details Multi-bank memory with word-line banking Multi-bank memory with word-line banking

1999-07-06

2000-07-04

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523004, 365203, G11C 800

Patent

active

060848197

ABSTRACT:
A multiple bank memory array includes a combined memory array, an X-decoder, a first word-line driver, a second word-line driver, a reference column, a Y-multiplexer and pre-charging circuit, a sense amplifier and input/output circuit, and control and precoding logic. Signals are received and applied to the combined memory array and the other components via the control and pre-decode logic and the input/output circuit. The control and pre-decode logic receives control signals to control and address the combined memory array, and uses a single bit for two dimensional decoding. This architecture for multiple bank memory cell arrays a novel technique for word-line banking in one embodiment that provides a combined array, does not require routing and eliminates redundant reference columns.

REFERENCES:
patent: 4849937 (1989-07-01), Yoshimoto
patent: 5287527 (1994-02-01), Delp et al.
patent: 5493535 (1996-02-01), Cho

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