Multi-bank integrated circuit memory devices having...

Details Multi-bank integrated circuit memory devices having... Multi-bank integrated circuit memory devices having...

2006-09-19

2006-09-19

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230030, C365S233500, C365S189020, C365S189030, C711S005000, C711S167000, C711S170000, C711S202000

Reexamination Certificate

active

07110321

ABSTRACT:
Integrated circuit memory devices support write and read burst modes of operation with uniformly short interconnect paths that provide high-speed memory access timing characteristics. These memory devices include a semiconductor chip having a memory core therein and at least N bond pads thereon. The memory core is configured to support a xN burst-M write mode of operation at QDR and/or DDR rates, where N is greater than four and M is greater than one. The memory core is further configured to support one-to-one mapping between burst-M write data received at each of the N bond pads and corresponding ones of N memory blocks in the memory core during the xN burst-M write mode of operation.

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Virtex, VTT008 (v2.0), High Speed Transceiver Logic (HSTL), May 5, 2001, pp. 1-7.

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