Multi-bank dRAM suitable for integration with processor on commo

Details Multi-bank dRAM suitable for integration with processor on commo Multi-bank dRAM suitable for integration with processor on commo

1997-02-10

1998-06-30

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36520308, G06F 1208

Patent

active

057744092

ABSTRACT:
A dynamic random access memory DRAM includes banks which are driven to active or inactive states independently of each other. Activation/inactivation of these banks are controlled by row controllers operating independently of each other, whereby a page or word line can be selected in each of the banks, a page hit rate can be increased, and the number of array precharge operation times in a page error as well as power consumption can be reduced in response. Thus, the cache hit rate of a processor having a built-in DRAM is increased and power consumption is reduced.

REFERENCES:
patent: 5553026 (1996-09-01), Nakai et al.
patent: 5617555 (1997-04-01), Patel et al.
patent: 5621690 (1997-04-01), Fungroth et al.
patent: 5644747 (1997-07-01), Kusuda
patent: 5663923 (1997-09-01), Baltar et al.

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