Multi-bank DRAM suitable for integration with processor on commo

Details Multi-bank DRAM suitable for integration with processor on commo Multi-bank DRAM suitable for integration with processor on commo

1998-05-18

1999-08-17

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523001, 36523009, 365239, 365240, G11C 700

Patent

active

059403420

ABSTRACT:
A dynamic random access memory DRAM includes banks which are driven to active or inactive states independently of each other. Activation/inactivation of these banks are controlled by row controllers operating independently of each other, whereby a page or word line can be selected in each of the banks, a page hit rate can be increased, and the number of array precharge operation times in a page error as well as power consumption can be reduced in response. Thus, the cache hit rate of a processor having a built-in DRAM is increased and power consumption is reduced.

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patent: 5652723 (1997-07-01), Dosaka et al.
patent: 5663923 (1997-09-01), Baltar et al.
patent: 5774409 (1998-06-01), Yamazako et al.

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