Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
1999-04-29
2001-05-15
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S049130, C365S230080, C365S230060
Reexamination Certificate
active
06233195
ABSTRACT:
RELATED APPLICATIONS
This application is related to U.S. application Ser. No. 08/500,039 filed Jul. 10, 1995, U.S. application Ser. No. 08/674,874 filed Jul. 2, 1996 and U.S. application Ser. No. 08/788,803 filed Jan. 23, 1997, all of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a control circuit therefor, and more particularly, it relates to a structure for efficiently accessing a semiconductor memory device in a circuit device including a processor and the semiconductor memory device which are integrated on a common semiconductor chip (substrate).
2. Description of the Background Art
FIG. 40
schematically illustrates the structure of a conventional microprocessor having a built-in main memory. Referring to
FIG. 40
, a DRAM (dynamic random access memory) serving as a main memory and a CPU (central processing unit) serving as a processor are integrated on a common semiconductor chip in the conventional microprocessor. This microprocessor further includes an SRAM (static random access memory) cache SCH for storing data/instructions relatively frequently accessed by the CPU for efficiently transferring data between the DRAM and the CPU, a data queue DTQ for queuing and storing the data used by the CPU, an instruction queue ITQ for queuing and storing the instructions executed by the CPU, a tag memory TGM for storing addresses of the data stored in the SRAM cache SCH, and a memory controller MCL for referring to the tag memory TGM in accordance with access requests from the CPU, determining whether or not required data/instructions are stored in the SRAM cache SCH and performing necessary control in accordance with the result of the determination.
The memory controller MCL controls data read/write operations of the instruction queue ITQ, the data queue DTQ and the SRAM cache SCH, while controlling reading/writing of data/instructions from/in the DRAM. The DRAM, the instruction queue ITQ, the data queue DTQ and the SRAM cache SCH are interconnected with each other by a data bus DBS. The memory controller MCL transmits commands for instructing necessary operations to the DRAM through a DRAM control bus CBS, and outputs addresses specifying accessed memory positions of the DRAM through a DRAM address bus ABS. The operation is now briefly described.
In accordance with an access request from the CPU, the memory controller MCL refers to the tag memory TGM in accordance with an address signal supplied together with this access request, and determines whether or not data access-requested by the CPU is present in the SRAM cache SCH. The tag memory TGM stores respective addresses (cache block (set) addresses) of a plurality of cache blocks stored in the SRAM cache SCH in tag address positions. The memory controller MCL supplies the tag memory TGM with a cache block address (set address) and a tag address in the address signal received from the CPU. The tag memory TGM reads the corresponding cache block address (set address) in accordance with the supplied tag address, and determines whether or not the read set address matches that supplied from the memory controller MCL. If the set addresses match each other, the tag memory TGM asserts a signal CH indicating a cache hit. If these addresses mismatch each other, on the other hand, the cache hit signal CH from the tag memory TGM is negated.
The memory controller MCL controls necessary data transfer in accordance with the cache hit/miss indication signal CH supplied from the tag memory TGM. In case of a cache hit, the memory controller MCL transfers the instruction/data access-requested by the CPU to the instruction queue ITQ or the data queue DTQ from the SRAM cache SCH. Then, the instruction queue ITQ or the data queue DTA supplies the instruction or the data to the CPU. After this transfer, the memory controller MCL transfers the remaining instructions/data of the access-requested cache block to the instruction queue ITQ or the data queue DTQ from the SRAM cache SCH at need.
In case of a cache miss, on the other hand, the memory controller MCL informs the CPU of the cache miss in which no necessary instruction/data is supplied if no usable instruction/data is present in the queue ITQ or DTQ, and temporarily interrupts the operation of the CPU. The memory controller MCL accesses the DRAM through the DRAM control bus CBS and the DRAM address bus ABS, and transfers a cache block including the data access-requested by the CPU to the SRAM cache SCH through the data bus DBS. In this data transfer, the DRAM transfers an instruction/data to the instruction queue ITQ or the data queue DTQ. Whether what is transferred is instruction or data is determined by a bit supplied from the CPU to the memory controller MCL. If an instruction/data is present in the instruction queue ITQ or the data queue DTQ during the data transfer from the DRAM to the queue ITQ or DTQ and the SRAM cache SCH, the memory controller MCL allows the CPU to access the instruction queue ITQ or the data queue DTQ. A penalty for the cache miss is reduced by using the queue.
As hereinabove described, necessary data of cache blocks stored in the SRAM cache SCH are queued and stored in the instruction queue ITQ and the data queue DTQ respectively through the fact that localization is present in address positions accessed by the CPU (successive addresses are sequentially accessed in a single processing), whereby necessary data can be transferred to the CPU at a high speed.
Further, the DRAM and the CPU are integrated and formed on the common semiconductor chip, whereby the data can be transferred between the DRAM, the instruction queue ITQ, the data queue DTQ and the SRAM cache SCH at a high speed. Namely, the line capacitance of the internal data bus DBS which is provided on the semiconductor chip is so small that the data can be transferred at a higher speed as compared with a case of employing a discrete DRAM. While data transfer is limited by the number of data input/output pin terminals in case of employing a discrete DRAM, a large quantity of data/instructions can be simultaneously transferred by employing the internal data bus DBS having a large bit width, whereby high-speed data transfer is implemented.
FIG. 41
schematically illustrates the internal structure of the DRAM shown in FIG.
40
.
Referring to
FIG. 41
, the DRAM includes a command latch
900
for latching a command supplied from the memory controller MCL through the DRAM control bus CBS in synchronization with a clock signal P
1
, an address latch
901
for latching an address signal supplied from the memory controller MCL through the DRAM address bus ABS in synchronization with the clock signal P
1
, a DRAM row controller
902
for decoding the command latched by the command latch
900
and generating a necessary control signal in accordance with the result of the decoding, a row address latch (row latch)
903
for latching an internal address signal Ad supplied from the address latch
901
in response to a row address latch instruction signal RAL from the DRAM controller
902
, a row predecoder
904
for predecoding a row address signal RA from the row address latch
903
and outputting a row selection signal X, a DRAM column controller
906
for decoding the command from the command latch
900
and outputting a control signal related to column selection in accordance with the result of the decoding, a column address latch (column latch)
908
for latching the internal address signal Ad supplied from the address latch
901
in response to a column address latch instruction signal CAL from the DRAM column controller
906
, a column predecoder
910
for predecoding an internal column address signal CA from the column address latch
908
and outputting a column selection signal Y, and a DRAM array
912
having dynamic memory cells arranged in a matrix.
This DRAM array
912
further includes a peripheral control circuit for sensing, amplifying and reading/writing data from/in a selected memory cell.
Dosaka Katsumi
Yamazaki Akira
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Viet Q.
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