Multi-array memory device, and associated method, having shared

Details Multi-array memory device, and associated method, having shared Multi-array memory device, and associated method, having shared

1998-07-08

2000-05-16

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365 63, 365 51, G11C 800

Patent

active

060646209

ABSTRACT:
A memory device, and an associated method, contains at least two memory arrays and a single decoder shared by the memory arrays. When data is to be accessed from selected memory locations of one of the memory arrays, the non-selected memory array is inactivated by precharging the bit lines of the array to a common voltage with the data input and/or output buses for that array, thereby allowing the decoder to select the inactive array without harm, and thereby preventing the need for additional decoder circuitry to discriminate between the arrays. The array containing the selected memory locations remains active, thereby permitting accessing of the memory locations therein.

REFERENCES:
patent: 5349552 (1994-09-01), Ampaglione
patent: 5687125 (1997-11-01), Kikuchi
patent: 5883848 (1999-03-01), Kim et al.

Affiliated with

Also associated with

Rating

Multi-array memory device, and associated method, having shared does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-array memory device, and associated method, having shared , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-array memory device, and associated method, having shared will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-264701