Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-03-23
2001-08-21
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060, C365S230080, C365S189120, C365S203000, C365S205000
Reexamination Certificate
active
06278646
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a memory device, such as a DRAM (dynamic random access memory) or enhanced dynamic random access memory (EDRAM® is a registered trademark of Enhanced Memory Systems, Inc.) having memory locations forming memory arrays. More particularly, the present invention relates to a multi-array memory device, and an associated method, by which decoder circuitry of the memory device is shared by more than one memory array.
In accordance with the present invention, because the bit decoder circuitry is shared by more than one memory array, separate bit decoders, conventionally associated with each memory array are not required. Thereby, the circuit area required to implement memory device is reduced relative to conventional multi-array memory devices. Through operation of an embodiment of the present invention, when memory locations of a selected memory array of the memory device are to be accessed, such as to perform read or write operations, the selected memory array becomes or remains active. All other memory arrays are driven to be inactive while biasing the write or input/output buses of the non-selected memory arrays to an inactive-array, bit-line, precharge voltage. In such manner, extra control lines are not required to activate, or inactivate, particular ones of the memory arrays.
The use of digital processing circuitry, and apparatus including such circuitry, to perform a wide range of functions is pervasive in modem society. Repetitive functions carried out by such circuitry can be performed at rates much more quickly than the corresponding functions performed manually. Functions can be performed, for instance, to process large amounts of data at a rapid rate. Such processing of data sometimes includes reading data from, or writing data to, memory devices.
A digital computer system, for example, includes a computer main memory which provides storage locations from which data can be read or to which data can be written. A computer main memory is typically formed of a plurality of memory devices which together form the main memory. The computer main memory, for instance, is sometimes formed of a number of asynchronous DRAM (dynamic random access memory) integrated circuits. Some conventional computer memories includes faster, SRAM (static random access memory) integrated circuits. SRAM devices permit quicker access to the memory locations thereof by making a high speed, locally-accessed copy of the memory available to the CPU (central processing unit) of the digital computer system.
Some computer systems include a computer main memory formed of EDRAM (enhanced dynamic random access memory; EDRAM™ is a trademark of Enhanced Memory Systems, Inc., Colorado Springs, Colo., assignee of the present invention). An EDRAM integrated circuit forms a memory device in which an static register (or SRAM row) component and a DRAM component are integrated onto a single integrated circuit chip. The advantages of a the improved access speeds of an SRAM device is provided to permit the CPU of the computer system to access the memory locations thereof at high access rates.
Such aforementioned memory devices are formed of memory locations which form memory arrays. The memory locations of the memory arrays are identified by memory addresses. When a memory location of a memory array is to be accessed, the address of the memory location is provided to decoder circuitry which decodes the address signals applied thereto to permit the access to the appropriate memory locations. Conventionally, separate decoder circuitry is associated with each memory array of a memory device. When memory locations of a memory array are to be accessed, address signals applied to the decoder circuitry permit the appropriate memory locations of the memory array associated with the particular decoder circuitry to be accessed.
A significant design goal in the design and implementation of an integrated circuit is the minimization of the circuit area required to implement the circuit. Any manner by which to reduce the circuit area required to implement the circuit would facilitate the miniaturization of the circuit. The conventional use of separate decoder circuitry associated with each array of a multi-array memory device requires significant circuit area for its implementation.
A manner by which to address memory locations of any selected memory array of a multi-array memory device without requiring the memory device to include separate decoder circuitry associated with each memory array would advantageously permit the reduction in circuit area required to implement the memory device. While some existing techniques have been developed which permit sharing of decoder circuitry between more than one memory array, such existing techniques typically require extra decoder circuitry, as well as extra address or command lines, to effectuate the sharing of decoder circuitry.
It is in light of this background information related to memory devices that the significant improvements of the present invention have evolved.
SUMMARY OF THE INVENTION
The present invention, accordingly, advantageously provides a multi-array, memory device, and an associated method, having bit decoder circuitry shared by more than one memory array of the memory device.
A memory device constructed according to the teachings of an embodiment of the present invention reduces the circuit area required for the implementation of the memory device as separate bit decoder circuitry need not be associated with each memory array. A single bit decoder circuit is shared by more than one memory array without the need of additional decoder circuitry or additional control lines. By removing the redundancy of the separate decoder circuitry associated with each of the memory arrays, the circuit area required to implement the memory device is reduced.
During operation of an embodiment of the present invention, when memory locations of a selected memory array of a multi-array memory device are to be accessed, any selected memory arrays becomes active, while all other memory arrays remain inactive. By biasing the write or input/output buses of the non-selected memory arrays to the same voltage as the bit lines of the non-selected memory arrays, the memory locations of only the active memory array are accessed. Extra control lines and extra control circuitry are not required.
In one implementation, a DRAM/SRAM row device containing multiple-writeable, memory arrays is provided. A single decoder is shared between the arrays. When write operations are to be performed upon selected memory locations of a particular one of the memory arrays, the selected memory array remains, or becomes, active while all non-selected memory arrays are caused to become inactive. The write buses of the non-selected memory arrays are set to the bit-line precharge voltage. Thereby, coupling of the buses to the bit lines through the action of the shared decoder, is not harmful, while the selected memory locations are accessed in the active array and the write operations are performed to write data to such selected memory locations.
In another implementation, a DRAM containing multiple-writeable, memory arrays is provided. A single decoder is shared between the arrays. When write operations are to be performed upon selected memory locations of a particular memory array, the selected memory array remains, or becomes, active while all non-selected memory arrays are caused to become inactive. The write buses of the non-selected memory arrays are set to the bit-line precharge voltage. Thereby, coupling of the buses to the bit lines through the action of the shared decoder is not harmful, while the selected memory locations are accessed in the active array and the write operations are performed to write data to such selected memory locations.
In these and other aspects, therefore, a memory device, and an associated method, for storing data therein is provided. The memory device includes a first memory array having a first plurality of memory locat
Enhanced Memory Systems Inc.
Hogan & Hartson LLP
Langley Stuart T.
Meza Peter J.
Nelms David
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