Modulators – Frequency shift keying modulator or minimum shift keying...
Reexamination Certificate
1999-04-28
2001-03-13
Mis, David (Department: 2817)
Modulators
Frequency shift keying modulator or minimum shift keying...
C375S305000
Reexamination Certificate
active
06201451
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an MSK (Minimum Shift Keying) modulator and an MSK modulation method, and more particularly to an MSK modulator and an MSK modulation method of transmitting data at high speed.
2. Description of the Related Art
An MSK modulation method has been widely employed as a technique for transmitting a digital signal. The well-known MSK modulation technique allows a phase of a (&pgr;/2) radian section (that is, for a quarter period) of a carrier wave to shift substantially :t (&pgr;/2) radians in a continuous manner, in accordance with a logic value of bits of a to-be-transmitted digital signal.
A conventional MSK modulator illustrated in
FIG. 6
for performing an MSK modulation is widely known.
The MSK modulator illustrated in
FIG. 6
includes a code generator
101
, phase shifters
102
to
104
, oscillators
105
and
106
, multipliers
107
to
110
and an adder
111
.
A to-be-transmitted digital signal generated by the code generator
101
is supplied to the multiplier
107
and to the phase shifter
102
. The phase of the digital signal supplied to the phase shifter
102
is delayed (&pgr;/2) radians so as the signal to be supplied to the multiplier
108
.
On the other hand, a reference signal of a sine wave or the like supplied from the oscillator
105
is supplied to the multiplier
107
and the phase shifter
103
. The phase of the reference signal supplied to the phase shifter
103
is delayed (&pgr;/2) radians, and the signal is supplied to the multiplier
108
.
The multiplier
107
generates a signal representing a product of the digital signal supplied from the code generator
101
and the reference signal supplied from the oscillator
105
, and supplies the generated signal to the multiplier
109
. The multiplier
108
generates a signal representing a product of the digital signal supplied from the phase shifter
102
and the reference signal supplied from the phase shifter
103
, and supplies the generated signal to the multiplier
110
.
A carrier wave of, for example, a sine wave supplied from the oscillator
106
is supplied to the multiplier
109
and the phase shifter
104
. The phase of the carrier wave supplied to the phase shifter
104
is delayed about (&pgr;/2) radians and the carrier wave itself is supplied to the multiplier
110
.
The multiplier
109
generates a signal representing a product of the signal supplied from the multiplier
107
and the carrier wave supplied from the oscillator
106
, so as to supply the generated signal to the adder
111
. The multiplier
110
generates a signal representing a product of the signal supplied from the multiplier
108
and the carrier wave supplied from the phase shifter
104
for supplying the generated signal to the adder
111
.
The adder
111
generates a signal representing a sum of signals supplied from the multipliers
109
and
110
. The adder
111
then outputs the generated signal as the MSK modulation wave having a carrier wave to which an MSK modulation is performed by a digital signal supplied from the code generator
101
.
In a case where the MSK modulator illustrated in
FIG. 6
includes analog circuits, the operations of the MSK modulator become unstable owing to a deviation of the operating characteristic in its analog circuits, a stray capacity, an inductance of the wiring or the like. For example, the degree to which the phase shifter causes the phase of the supplied signal to shift may not substantially be (&pgr;/2) radians. The higher the frequency of a phase shifted signal, the more the above phenomenon. In order to overcome the above problems, there is provided a method in which at least a part of the MSK modulator is made of a digital circuit, as disclosed, for example, in the Laid-Open JP Application Kokai No. Heisei 5-63742.
According to the method disclosed in the Laid-Open JP Application Kokai No, Heisei 5-63742, a pair of base band signals which are out of phase from each other by (&pgr;/2) radians are converted from series to parallel. The pair of base band signals are generated in a manner by which to-be-transmitted digital signals delay by using a ½ data delay circuit. The base band signals converted as parallel signals are supplied to an RAM (Random Access Memory) designated by a timing generating circuit, as address data.
The RAM stores various data showing a multiplication result of a master clock and base band signals converted to parallel signals, in its storage region where the value of the base band signals is recognized as an address. When the base band signals as address data are supplied, the RAM outputs the data representing its product.
According to the technique of the Laid-Open JP Application Kokai No. Heisei 5-63742, in a case where a digital signal is transmitted at a speed of, for example, ten megasamples per second, an accurate modulation can not be performed unless the RAM may possibly read out the data at speed as the following data is converted without delay.
In order to enhance conversion accuracy, a large number of patterns of the multiplication result stored in the RAM needs to be arranged. The number of bits of the digital signals converted in parallel at once needs to be larger. Further, it is inevitable that the memory capacity of the RAM needs to be large and the structure of the circuit converting the signals from series to parallel needs to be complex. As a result, the structure of the device becomes even more complicated and large scale.
A method of generating the pair of base band signals as employed in the JP Patent No. Heisei 5-63742, there can be considered a method of using an analog circuit for allowing the phase of a signal to shift, or using a digital signal processing device such as a DSP (Digital Signal Processor) capable of calculating complex numbers for applying a phase shifting.
In the case where the phase of the signal is shifted by using an analog circuit, the problematic phenomenon as explained above arises as the degree to which the phase of the signal shifts may not substantially be (&pgr;/2) radians. It is extremely difficult to keep away from this problematic phenomenon, in a case where the phase shift is performed in terms of the signal including data of ten megasamples per second.
In a case where the digital signal processing device is to calculate complex numbers, the phase shift is not appropriately performed, for data is supplied at a high speed exceeding the calculation speed of the digital signal processing device. Therefore, the phase of the signal including the data of ten megasamples per second is absolutely difficult to be shifted by a calculation of the digital signal processing device.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above, and an object thereof is to provide an MSK modulator and MSK modulation method of performing an MSK modulation accurately by using high speed data in digital form, and provided the systematic structure for enabling an MSK modulation accurately by using high speed data in digital form.
In order to achieve the above-described object, according to the first aspect of the present invention, there is provided an MSK modulator comprising:
a digital signal generator (
2
) which generates a first digital signal representing a first analog signal representing logic values of bits of a to-be-modulated digital signal in accordance with a (&pgr;/2) radian-phase delay or advance of a carrier wave at a predetermined time, and a second digital signal representing a second analog signal which is substantially out of phase about (&pgr;/2) radians with respect to the first analog signal;
a digital-to-analog converter (
3
I,
3
Q) which obtains the first and second digital signals from the digital signal generator so as to convert each of the signals into an analog signal respectively and generates the first and second analog signals; and
an orthogonal modulator (
6
I,
6
Q,
7
,
8
and
9
) which obtains the first and second analog signals from the digital-to-analog conve
Frishauf, Holtz Goodman, Langer & Chick, P.C.
Mis David
UCOM Incorporated
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