MRAM with asymmetric cladded conductor

Details MRAM with asymmetric cladded conductor MRAM with asymmetric cladded conductor

2002-11-13

2004-05-25

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Magnetic field

C257S422000, C257S428000, C257S775000, C365S171000, C365S173000

Reexamination Certificate

active

06740947

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a magnetic memory device in which at least one of the conductors includes an asymmetric cladding. More specifically, the present invention relates to a magnetic memory device in which at least one of the conductors includes an asymmetric cladding that is recessed to minimize undesirable effects to a switching characteristics of a data layer of a magnetic memory cell while providing for switching field enhancement.
BACKGROUND OF THE ART
Magnetic Random Access Memory (MRAM) is an emerging technology that can provide an alternative to traditional data storage or memory technologies. MRAM has desirable properties such as fast access times like DRAM and non-volatile data retention like hard disc drives. MRAM stores a bit of data (i.e. information) as an alterable orientation of magnetization in a patterned thin film magnetic element that is referred to as a data layer, a storage layer, a free layer, or a data film. The data layer is designed so that it has two stable and distinct magnetic states that define a binary one (“1”) and a binary zero (“0”). Although the bit of data is stored in the data layer, many layers of carefully controlled magnetic and dielectric thin film materials are required to form a complete magnetic memory element. One prominent form of magnetic memory element is a spin tunneling device. The physics of spin tunneling is complex and good literature exists on this subject.
In
FIG. 1
a
, a prior MRAM memory element
101
includes a data layer
102
and a reference layer
104
that are separated by a thin barrier layer
106
. Typically the barrier layer
106
has a thickness that is less than about 2.0 nm. The memory element
101
has a width W and a length L and a ratio of the width W to the length L defines an aspect ratio (i.e. aspect ratio=W÷L). In a tunneling magnetoresistance memory (TMR) the barrier layer
106
is an electrically non-conductive dielectric material such as aluminum oxide (Al
2
O
3
), for example. Whereas, in a giant magnetoresistance memory (GMR) the barrier layer
106
is a thin layer of conductive material such as copper (Cu), for example. The reference layer
104
has a pinned orientation of magnetization
108
, that is, the pinned orientation of magnetization
108
is fixed in a predetermined direction and does not rotate in response to an external magnetic field. In contrast the data layer
102
has an alterable orientation of magnetization
103
that can rotate between two orientations in response to an external magnetic field. The alterable orientation of magnetization
103
is typically aligned with an easy axis E of the data layer
102
.
In
FIG. 1
b
, when the pinned orientation of magnetization
108
and the alterable orientation of magnetization
103
point in the same direction (i.e. they are parallel to each other) the data layer
102
stores a binary one (“1”). On the other hand, when the pinned orientation of magnetization
108
and the alterable orientation of magnetizations
103
point in opposite directions (i.e. they are anti-parallel to each other) the data layer
102
stores a binary zero (“0”).
In
FIG. 2
a
, the prior memory element
101
is typically positioned at an intersection of two orthogonal conductors
105
and
107
. For instance, the conductor
105
can be a word line and the conductor
107
can be a bit line. Collectively, the conductors (
105
,
107
) can be called write lines. A bit of data is written to the memory element
101
by generating two magnetic fields H
x
and H
y
that are in turn generated by currents I
y
and I
x
flowing in the conductors
107
and
105
respectively. The magnetic fields H
x
and H
y
cooperatively interact with the data layer
102
to rotate the alterable orientation of magnetization
103
from its current orientation to a new orientation. Therefore, if the current orientation is parallel (i.e. a positive X-direction on a x-axis X) with the pinned orientation of magnetization
108
such that a binary “1” is stored in the data layer
102
, then the magnetic fields H
x
and H
y
will rotate the alterable orientation of magnetization
103
to an anti-parallel orientation (i.e. a negative X-direction on the x-axis X) such that a binary “0” is stored in the data layer
102
.
In
FIG. 2
a
, the alterable orientation of magnetization
103
is illustrated in the process of rotating from the positive X-direction to the negative X-direction. Both of those directions are aligned with the easy axis E. However, during the rotation, the alterable orientation of magnetization
103
will be temporarily aligned with a hard axis H that is aligned with a positive Y-direction and a negative Y-direction of a y-axis Y.
In
FIG. 2
b
, the prior memory element
101
is positioned in an array
201
of similar memory elements
101
that are also positioned at an intersection of a plurality of the conductors
107
and
105
that are arranged in rows and columns. For purposes of illustration, in
FIG. 2
b
, the conductors
107
are bit lines and the conductors
105
are word lines. A bit of data is written to a selected one of the memory elements
101
that is positioned at an intersection of a word and bit line by passing the currents I
y
and I
x
through the word and bit lines. During a normal write operation, the selected memory element
101
will be written to only if the combined magnetic fields H
x
and H
y
are of a sufficient magnitude to switch (i.e. rotate) the alterable orientation of magnetization of the memory element
101
.
In
FIG. 3
a
, when the alterable orientation of magnetization
103
is aligned with the easy axis E, the prior data layer
102
will have magnetic charges, denoted as a plus sign+and a minus sign−, and those magnetic charges (+, −) generate a demagnetization field H
DE
. The demagnetization field H
DE
facilitates switching of the data layer
102
by reducing a magnitude of the combined magnetic fields (H
x
, H
y
) that are required to rotate the alterable orientation of magnetization
103
. Essentially, the amount of energy required to rotate the alterable orientation of magnetization
103
is reduced.
Similarly, in
FIG. 3
b
, when the alterable orientation of magnetization
103
is in a partially rotated position that is parallel to the hard axis H, another demagnetization field H
Dh
is generated by magnetic charges (+, −). Those magnetic charges oppose further rotation of the alterable orientation of magnetization
103
.
The switching characteristics of the data layer
102
are determined in part by the magnitudes of the demagnetization fields (H
DE
, H
Dh
). Preferably, the magnitude of the demagnetization field H
DE
is sufficient to reduce the amount of energy required to initiate rotation of the alterable orientation of magnetization
103
and the magnitude of the demagnetization field H
Dh
is sufficient to slightly resist further rotation of the alterable orientation of magnetization
103
so that as the alterable orientation of magnetization
103
passes through the hard axis H, the data layer
102
does not immediately switch (i.e from a logic “1” to a logic “0”).
One of the disadvantages of prior MRAM designs is that the currents (I
y
, I
x
) that are required to generate the combined magnetic fields (H
x
, H
y
) are too high. High current is undesirable for several reasons. First, high currents increase power consumption which is undesirable in portable electronics or battery powered electronics. Second, high currents can result in increase waste heat generation which can require fans or other cooling devices to efficiently dissipate the waste heat. Those cooling devices add to the cost, weight, and power drain in battery operated devices. Third, larger drive circuits are required to source those high currents and the larger drive circuits reduce an amount of die area available for memory or other critical circuits in a memory device. Finally, the conductors that carry the current can fail due to electromigration caused by a high curren

Affiliated with

Also associated with

Rating

MRAM with asymmetric cladded conductor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MRAM with asymmetric cladded conductor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MRAM with asymmetric cladded conductor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3244840