MRAM layer having domain wall traps

Details MRAM layer having domain wall traps MRAM layer having domain wall traps

2007-09-11

2007-09-11

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C257SE43006, C257SE27006, C257SE21665

Reexamination Certificate

active

11325155

ABSTRACT:
A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

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