MRAM internal clock pulse generation with an ATD circuit and...

Details MRAM internal clock pulse generation with an ATD circuit and... MRAM internal clock pulse generation with an ATD circuit and...

2006-09-11

2009-02-10

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100, C365S230010

Reexamination Certificate

active

07489589

ABSTRACT:
A magnetic random access memory having an extended address transition detection circuit having a chip enable input, a chip write enable input, a data bus connection, and an address bus connection. The extended address transition detection circuit has an extended transition detection signal output. The magnetic random access memory has a timing controller with a timing control input connected to the address transition detection signal output. The chip enable input, the chip write enable input, the data bus connection, and the address bus connection are buffered and driven off chip.

REFERENCES:
patent: 5548560 (1996-08-01), Stephens et al.
patent: 6075750 (2000-06-01), Campardo et al.

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