Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Magnetic field
Reexamination Certificate
2003-09-23
2004-11-02
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Magnetic field
C257SE27006, C257S295000
Reexamination Certificate
active
06812538
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to magnetic memories, and more particularly to a method and system for providing a magnetic random access memory (MRAM) that is preferably high density, nonvolatile and that incorporates write-lines having improved writing efficiencies, ease of manufacturing, and better reliability against electromigration.
BACKGROUND OF THE INVENTION
Recently, a renewed interest in thin-film magnetic random access memories (MRAM) has been sparked by the potential application of MRAM to both nonvolatile and volatile memories.
FIG. 1
depicts a portion of a conventional MRAM
1
. The conventional MRAM includes conventional orthogonal conductor lines
10
and
12
, conventional magnetic storage cell
11
and conventional transistor
13
. The conventional MRAM
1
utilizes a conventional magnetic tunneling junction (MTJ) stack
11
as a memory cell. Use of a conventional MTJ stack
11
makes it possible to design an MRAM cell with high integration density, high speed, low read power, and soft error rate (SER) immunity. The conductive lines
10
and
12
are used for writing data into the magnetic storage device
11
. The MTJ stack
11
is located on the intersection of and between
10
and
12
. Conventional conductive line
10
and line
12
are referred to as the conventional word line
10
and the conventional bit line
12
, respectively. The names, however, are interchangeable. Other names, such as row line, column line, digit line, and data line, may also be used.
The conventional MTJ
11
stack primarily includes the free layer
1104
with the changeable magnetic vector (not explicitly shown), the pinned layer
1102
with the fixed magnetic vector (not explicitly shown), and the insulator
1103
in between the two magnetic layers
1104
and
1102
. The insulator
1103
typically has a thickness that is low enough to allow tunneling of charge carriers between the magnetic layers
1102
and
1104
. Layer
1101
is usually a composite of seed layers and an anti-ferromagnetic layer that is strongly coupled to the pinned magnetic layer.
Data is stored in the conventional MTJ stack
11
by applying a magnetic field to the conventional MTJ stack
11
. The applied magnetic field has a direction chosen to move the changeable magnetic vector of the free layer
1104
to a selected orientation. During writing, the electrical current I
1
flowing in the conventional bit line
12
and I
2
flowing in the conventional word line
10
yield two magnetic fields on the free layer
1104
. In response to the magnetic fields generated by the currents I
1
and I
2
, the magnetic vector in free layer
1104
is oriented in a particular, stable direction. This direction depends on the direction and amplitude of I
1
and I
2
and the properties and shape of the free layer
1104
. Generally, writing a zero (0) requires the direction of either I
1
or I
2
to be different than when writing a one (1). Typically, the aligned orientation can be designated a logic 1 or 0, while the misaligned orientation is the opposite, i.e., a logic 0 or 1, respectively.
Stored data is read or sensed by passing a current through the conventional MTJ cell from one magnetic layer to the other. During reading, the conventional transistor
13
is turned on and a small tunneling current flows through the conventional MTJ cell. The amount of the current flowing through the conventional MTJ cell
11
or the voltage drop across the conventional MTJ cell
11
is measured to determine the state of the memory cell. In some designs, the conventional transistor
13
is replaced by a diode, or completely omitted, with the conventional MTJ cell
11
in direct contact with the conventional word line
10
.
Although the above conventional MTJ cell
11
can be written using the conventional word line
10
and conventional bit line
12
, one of ordinary skill in the art will readily recognize that the amplitude of I
1
or I
2
is in the order of several milli-Amperes for most designs. Therefore, one of ordinary skill in the art will also recognize that a smaller writing current is desired for many memory applications.
FIG. 2
depicts a portion of a conventional magnetic memory
1
′ that has a lower writing current. Similar systems are described in U.S. Pat. No. 5,659,499, U.S. Pat. No. 5,940,319, U.S. Pat. No. 6,211,090, U.S. Pat. No. 6,153,443, and U.S. Patent Application Publication No. 2002/0127743. The conventional systems and conventional methods for fabricating the conventional systems disclosed in these references encapsulate bit lines and word lines with soft magnetic cladding layer on the three surfaces not facing MTJ cell
11
′. Many of the portions of the conventional memory depicted in
FIG. 2
are analogous to those depicted in FIG.
1
and are thus labeled similarly. The system depicted in
FIG. 2
includes the conventional MTJ cell
11
′, conventional word line
10
′ and bit line
12
′. The conventional word line
10
′ is composed of two parts: a copper core
1001
and a soft magnetic cladding layer
1002
. Similarly, the conventional bit line
12
′ is composed of two parts: a copper core
1201
and a soft magnetic cladding layer
1202
.
Relative to the design in
FIG. 1
, the soft magnetic cladding layers
1002
and
1202
can concentrate the magnetic flux associated with I
1
and I
2
onto the MTJ cell
11
′ and reduce the magnetic field on the surfaces which are not facing the MTJ cell
11
′. Thus, the sot magnetic cladding layers
1002
and
1202
concentrate the flux on the MTJ that makes up the MTJ cell
11
′, making the free layer
1104
easier to program.
Although this approach works theoretically, one of ordinary skill in the art will readily recognize that the magnetic properties of the portions of the soft cladding layers
1002
and
1202
on the vertical sidewalls of the conventional lines
10
′ and
12
′, respectively, are hard to control. One of ordinary skill in the art will also recognize that the process of making the conventional word line
10
′ and the conventional bit line
12
′ is complicated. Formation of the conventional word line
10
′ and conventional bit line
12
′ including the cladding layers
1002
and
12002
, respectively, requires approximately nine thin film deposition steps, five photolithography steps, six etching steps, and one chemical mechanical polishing (CMP) step. Furthermore, none of the processes can be shared with other CMOS processes. Some of the processes, such as the CMP process and a few thin-film deposition and etching processes, need to be tightly controlled in order to achieve the designed performance. Because the wafer surface on which the devices are fabricated is not flat and the portion to be removed is deep in the trenches, the write lines
10
′ and
12
′ need to be laid out fairly sparsely to accommodate the photolithography process. As a consequence, the density and capacity of memory devices on a chip will be sacrificed if soft magnetic cladding layer
1202
and
1002
is used for the lines
10
′ and
12
′. This complicated fabrication methods pose significant challenge to scaling to higher densities. Accordingly it is highly desirable to provide an MRAM architecture which is scalable, easy to fabricate, and offers high writing efficiency.
Other aspects of the conventional write lines
10
,
10
′,
12
, and
12
′ of the conventional designs depicted in both FIG.
1
and
FIG. 2
limit scalability. In these conventional designs, the conventional write lines
10
,
10
′,
12
, and
12
′are mostly made of either aluminum or copper. The current density limits for aluminum and copper are in the order of 1×10
6
A/cm
2
or less. As the line width decreases to increase the memory density, the electromigration current density limit poses severe challenges for scaling.
Other conventional systems attempt to propose different solutions, each of which has its drawbacks. As an example, U.S. Pate
Applied Spintronics Technology, Inc.
Ho Tu-Tu
Nelms David
Sawyer Law Group LLP
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