MRAM cell with flat topography and controlled bit line to...

Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Magnetic field

Reexamination Certificate

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C257SE27006, C257S295000

Reexamination Certificate

active

06969895

ABSTRACT:
A method for forming MRAM cell structures wherein the topography of the cell is substantially flat and the distance between a bit line and a magnetic free layer, a word line and a magnetic free layer or a word line and a bit line and a magnetic free layer is precise and well controlled. The method includes the formation of an MTJ film stack over which is formed both a capping and sacrificial layer. The stack is patterned by conventional means, then is covered by a layer of insulation which is thinned by CMP to expose a remaining portion of the sacrificial layer. The remaining portion of the sacrificial layer can be precisely removed by an etching process, leaving only the well dimensioned capping layer to separate the bit line from the magnetic free layer and the capping layer. The bit line and an intervening layer of insulation separate the free layer from a word line in an equally precise and controlled manner.

REFERENCES:
patent: 6174737 (2001-01-01), Durlam et al.
patent: 6548849 (2003-04-01), Pan et al.
patent: 6680500 (2004-01-01), Low et al.
patent: 6704220 (2004-03-01), Leuschner
patent: 6744608 (2004-06-01), Sin et al.
patent: 2004/0109339 (2004-06-01), Tsang

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