MRAM bit line word line architecture

Details MRAM bit line word line architecture MRAM bit line word line architecture

2001-09-27

2003-06-24

Tran, M. (Department: 2818)

Static information storage and retrieval

Read only systems

Magnetic

C365S066000

Reexamination Certificate

active

06584006

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to semiconductor memory devices and more particularly to a random access memory architecture having lowered bit and word line resistance across the architecture.
BACKGROUND OF THE INVENTION
Traditional memory devices, such as DRAM and FLASH memory devices, generally include an array of word and bit lines that intersect to form an array. At each intersection is coupled a memory cell. Programming current can be provided to the word and bit lines that correspond to the desired memory cell in order to write data to or read data from the memory cell. Magnetic random access memory (MRAM) devices are an emerging technology which provide numerous benefits over DRAM and FLASH memory devices such as non-volatility in contrast to the DRAM device, and faster operation, in contrast to the FLASH memory devices.
In traditional memory devices, the length of the word and bit lines that form the array is not typically a design concern. However, the resistance across the bit and word lines is of particular concern in magnetic random access memory (MRAM) devices because the programming current in MRAM devices is higher than in traditional memory devices. The length of the bit and word lines is restricted by the resistance of the lines when the programming current is propagated through the lines. While longer word and bit lines provide larger arrays and better efficiency, the longer word and bit lines have high resistance that results in an excessive voltage drop and undesirable heat generation.
In MRAM devices, high resistance across the word and bit lines can cause several problems. One problem is a resulting voltage drop across bit and word lines. If the voltage falls outside of an operating voltage range the memory cell could be damaged.
SUMMARY OF THE INVENTION
These and other problems are generally solved or circumvented, and technical advantages are generally achieved by the present invention, which in one embodiment provides a random access memory architecture.
In one preferred embodiment memory device of the present invention, the device comprises a plurality of bit lines and a plurality of word lines. The plurality of word lines form a cross-point array with the plurality of bit lines. One of a plurality of memory cells is located at each of the cross-points in the array. A bit decoder having a current source and current sink is coupled to the bit lines and a word decoder having a current source and a current sink is coupled to the word lines. A first series of switch circuits are coupled to two adjacent bit lines. The first series of switch circuits are located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines. The memory cell at the corresponding cross-point is selected for writing when the corresponding bit and word lines are provided with a predetermined amount of current.
In another preferred embodiment, the switch circuits are located along the word lines. In yet another embodiment, the memory device will utilize a first series of switch circuits along the bit lines and a second series of switch circuits are coupled to two adjacent word lines. The second series of switch circuits are located along the adjacent word lines resulting in the array being divided into segments along the adjacent word lines.
One advantage of a preferred embodiment of the present invention is that it reduces the resistance across word and bit lines which limit bit and word line length.
Another advantage of a preferred embodiment of the present invention is that it uses an easily implemented switch circuit to reduce resistance across the word and bit lines.
A further advantage of a preferred embodiment of the present invention is that some of the architecture of the preferred embodiment can be located beneath the array to reduce the amount of physical space needed.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the concepts and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.


REFERENCES:
patent: 4498154 (1985-02-01), Hoffmann
patent: 5388068 (1995-02-01), Ghoshal et al.
patent: 5506813 (1996-04-01), Mochizuki et al.
patent: 5943284 (1999-08-01), Mizuno et al.
patent: 6111783 (2000-08-01), Tran et al.

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