MR head read amplifier with improved write to read recovery...

Dynamic magnetic information storage or retrieval – General recording or reproducing – Specifics of biasing or erasing

Reexamination Certificate

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Details

C360S067000, C360S062000

Reexamination Certificate

active

06219194

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
Not Applicable
REFERENCE TO MICROFICHE APPENDIX
Not Applicable
FIELD OF THE INVENTION
The present invention relates to systems for reading stored data, and more particularly, to systems that utilize a magneto-resistive head to read data recorded on magnetic media.
BACKGROUND OF THE INVENTION
High-capacity computer storage devices typically include one or more electro-magnetic transducers and a corresponding number of magnetic media disks. The transducers, also known in the art as “heads,” are adapted for transfer of electronic information between a data source, for example a computer, and data locations on the magnetic disks. Information is communicated in accordance with well-known conventions and formats that enable high-density storage, rapid access to data locations, high reliability, data integrity, and device miniaturization. A magneto-resistive (hereinafter referred to as MR) head is one of several types of electro-magnetic transducers known in the art. In general, an MR head includes an inductive component to write data and an MR sensor component to read data from magnetic media. In order to be active, the MR sensor requires an electrical bias current I
B
during the reading process. This bias current I
B
generally needs to be turned off during the writing process.
FIG. 1
illustrates a simplified schematic of a prior art circuit
10
for generating a bias current I
B
for an MR sensor and for amplifying the underlying read signal produced by the MR head.
FIG. 2
illustrates a number of curves representing various time varying voltages from the circuit
10
of FIG.
1
.
In this prior art system, the MR sensor
12
is differentially AC coupled through capacitors
14
and
16
of value C to the read amplifier (READ AMP)
18
. A biasing network including resistors
20
and
22
of value R supply DC biasing to the inputs of amplifier
18
. Operational Amplifiers (OP AMPs)
24
and
26
provide the bias current through MR sensor
12
by developing a differential voltage across the series combination of resistors
28
and
30
and MR sensor
12
which has an equivalent resistance value of R
MR
. When the bias enable switch
32
is closed, the voltage developed by the DAC
34
is amplified by the OP AMPs
24
and
26
to produce voltage +V
B
at the top of R
B
28
and −V
B
at the bottom of R
B
30
. This results in the bias current I
B
as follows:
I
B
=
2

V
B
(
2

R
B
+
R
MR
)
Because the voltage developed by the two Operational Amplifiers
24
and
26
is differential, the common-mode voltage V
MR
across the MR head
12
is close to ground potential so as to prevent electrostatic discharge (ESD) damage to the MR head. The absolute value of the bias current I
B
can be adjusted by changing the voltage at the output of DAC
34
to fit the precise MR sensor and magnetic media characteristics.
The Bias Enable Switch
32
turns the bias current I
B
off during the write operation and turns I
B
on during the read operations. Turning on I
B
at the beginning of the read operation produces an undesired voltage transient at the differential input terminals of the READ AMP
18
, as illustrated by curve
56
in FIG.
2
. The switch
32
closes at time t=T
0
, applying the output voltage of DAC
34
to the inputs of the OP AMPs
24
and
26
, as shown by curve
50
. The DAC output voltage is amplified to produce the differential voltage represented by curve
52
across the outputs of OP AMPs
24
and
26
. This differential voltage (driven across the series network of two bias resistors
28
and
30
and the MR sensor
12
) results in a bias current I
B
through the MR sensor
12
. The current I
B
flowing through the MR sensor
12
develops voltage V
MR
represented by curve
54
across the MR sensor
12
. A typical value of the MR sensor resistance (R
MR
) is 40 ohms, and a typical value of bias current I
B
is 10 mA; thus the voltage V
MR
developed across the MR sensor
12
when the switch
32
is closed may be expected to be on the order of 400 mV, with a relatively fast rise time because of a relatively small time constant. The inputs of the READ AMP
18
are capacitively coupled to the MR sensor
12
to block the DC voltage, while providing a path for a read signal from the MR sensor
12
having a bandwidth from a few hundred KHz (e.g., 300 KHz). To minimize distortion of low frequency components of the read signal, the time constant T
C
of the READ AMP input must be fairly large, on the order of 50 microseconds. The time constant T
C
may be determined from the following equation (approximately, considering that R
MR
is relatively small):
T
C
=
(
2

R
)
×
C
2
=
RC
After t=T
0
, a voltage transient is superimposed on the read signal from the MR sensor
12
across the inputs of the READ AMP
18
, as represented by curve
56
shown in FIG.
2
. The transient decays exponentially as expressed by the following equation:
V
RD
=

-


(
i
-
T
0
)
T
C
This decay is unacceptably long because it causes the head amplifier to saturate. Since a saturated head amplifier distorts the underlying read signal from the MR sensor
12
, a significant portion of the magnetic track is wasted; the system can not effectively process the read signal until the transient sufficiently decays and the head amplifier returns to its linear operating region. It is therefore desirable to reduce the length of the transient to as short a duration as possible.
It is an object of the present invention to substantially overcome the above-identified disadvantages and drawbacks of the prior art.
SUMMARY OF THE INVENTION
The foregoing and other objects are achieved by the invention which in one aspect comprises an apparatus for substantially eliminating a switching voltage transient in a magnetic recording system so as to minimize a write-to-read recovery time. The magnetic recording system includes a first bias enable switch, a bias current source responsive to the first bias enable switch, an MR sensor for receiving a bias current from the current source, and a read amplifier being capacitively coupled to the MR sensor. The bias current flowing through the MR sensor produces the switching voltage transient. The apparatus includes a first compensating circuit for generating a compensating voltage transient having a polarity substantially equal and opposite to the switching transient. The first compensating circuit is electrically coupled to the MR sensor, and a superposition of the switching voltage transient and the compensating voltage transient is substantially zero.
In another embodiment, the first compensating circuit includes a first voltage source that produces a first output voltage responsive to the first bias enable switch. The first compensating circuit also includes a first conditioning circuit for applying an offset to the first output voltage and for varying an amplitude of the first output voltage, so as to produce a first conditioned voltage. The first compensating circuit further includes a first voltage-to-current converter for producing a first compensating current corresponding to the conditioned voltage. The first voltage-to-current converter is electrically coupled to the MR sensor such that the first compensating current is drawn from the bias current source.
In another embodiment, the bias current source supplies additional current drawn by the first compensating circuit, such that the first compensating circuit does not reduce the bias current flowing through the MR sensor.
In another embodiment, the first voltage source includes a digital-to-analog converter electrically coupled to a second bias enable switch. In this embodiment, the second bias enable switch is responsive to the first bias enable switch. In alternative embodiments, the two switches change state at the same time and the state of the second switch is always the same as the state of the first switch.
In another embodiment, the apparatus includes a second com

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