MPSK demodulator

Details MPSK demodulator MPSK demodulator

1995-07-31

1999-01-19

Tse, Young T.

Pulse or digital communications

Receivers

Angle modulation

375324, 375329, 329304, H04L 2722

Patent

active

058621873

ABSTRACT:
A receiver for decoding passband signal pulses transmitted in accordance with a M-ARY phase shift keying modulation scheme, comprises a multiphase sampler for sampling received passband signal pulses in the passband frequency range so as to generate a plurality of digital words corresponding to the sampled passband signal pulses, such that each digital word represents the phase of each sampled passband signal pulse. A phase reference register or other storage device is coupled to the multiphase sampler for storing one of the digital words as a phase reference such that other digital words generated by the multiphase sampler are compared with the digital word corresponding to the phase reference for decoding the passband signal pulses.

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"A 2.5-Gb/sec 15-mW BiCMOS Clock Recovery Circuit", AT&T By: Behzad Rasavi and James Sung.
WP 3.6:"A 500MHz Time Digitizer IC with 15.625ps Resolution" By:T. Knotts, D. Chu, J.
"A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-um CMOS" By: B. Kim,D. Helman, P. Gray, IEEE Dec. 1990, pp. 1385-1394.
Session 11: High-Sped Communication IC's FAm 11.5: A Monolithic CMOS 10MHz DPLL for Burst-Mode Data Retiming By: Jeff Sourrley and Robert Loonowich.
WP 3.2: A CMOS Multi-Channel IC for Pulse Timing Measurements with 1mV Sensitivity By: M> Loinaz and B. Wooley.
Session 11: High-Speed communication IC's FAM 11.5 A Monolithic CMOS 10MHz DPLL for Burst-Mode Data Retiming By: Jeff Sourrley and Robert Loonowich.
WP 3.2: A CMOS Multi-Channel IC for Pulse Timing Measurements with 1mV Sensitivity by: Loinaz, J. and Wooley, Bruce A.

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