Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1999-01-25
2002-10-22
Le, Vu (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C375S240250
Reexamination Certificate
active
06470051
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application contains subject matter which is related to the subject matter of the following United States patent applications, which are assigned to the same assignee of this application. Each of the below listed applications is hereby incorporated herein by reference:
“Anti-Flicker Logic For MPEG Video Decoder With Integrated Scaling and Display Functions,” by D. Hrusecky, co-filed herewith, Ser. No. 09/237,600;
“Multi-Format Reduced Memory MPEG-2 Compliant Decoder,” by Cheney et al., Ser. No. 08/958,632;
“Multi-Format Reduced Memory Video Decoder With Adjustable Polyphase Expansion Filter,” by D. Hrusecky, Ser. No. 09/015,463, which is a continuation-in-part application from pending U.S. patent application “Multi-Format Reduced Memory MPEG-2 Compliant Decoder,” by Cheney et al., Ser. No. 08/958,632;
“Multi-Format Reduced Memory MPEG Decoder With Hybrid Memory Address Generation,” by Cheney et al., Ser. No. 09/014,896, which is a continuation-in-part application from pending U.S. patent application “Multi-Format Reduced Memory MPEG-2 Compliant Decoder,” by Cheney et al., Ser. No. 08/958,632; and
“Compression/Decompression Engine For Enhanced Memory Storage In MPEG Decoder,” by Buerkle et al., Ser. No. 08/971,438.
TECHNICAL FIELD
The present invention is directed generally to digital video signal processing, and more particularly, to integrated decode systems, methods and articles of manufacture which allow selective scaling of video presentation by a predetermined reduction factor, while at the same time allowing for reduced external memory requirements for frame buffer storage.
BACKGROUND OF THE INVENTION
The MPEG-2 standard describes an encoding method that results in substantial bandwidth reduction by a subjective lossy compression followed by a lossless compression. The encoded, compressed digital data is subsequently decompressed and decoded in an MPEG-2 compliant decoder. Video decoding in accordance with the MPEG-2 standard is described in detail in commonly assigned U.S. Pat. No. 5,576,765, entitled “Video Decoder”, which is hereby incorporated herein by reference in its entirety.
Video decoders are typically embodied as general or special purpose processors and memory. For a conventional MPEG-2 decoder, two decoded reference frames are typically stored in memory at the same time. Thus, the cost of memory can often dominate the cost of the decode system. For example, an MPEG-2 video decoder might employ 2 MB or more of external memory, which generally comprises Dynamic Random Access Memory (DRAM). External memory is used for various data areas, or buffers such as frame buffers.
In practice, the MPEG-2 video decoder is typically limited to 2 MB of external memory in order to minimize cost of the end product. The decoder must perform all of its functions within this limitation. For example, of particular importance is enabling output for both the European market which utilizes the PAL standard of 576 video scan lines and the U.S. market which utilizes the NTSC standard of 480 video scan lines. Even if there is no 2 MB of external memory limitation, it is advantageous to perform the video decode and display in as small a memory space as possible in order to give the remaining memory to other built-in features, such as on-screen graphics.
The MPEG-2 decompressed video data buffers, also called frame buffers, consume the largest part of external DRAM, therefore they are the prime candidate for memory reduction/compression. The frame buffers contain final pixel display and MPEG-reference data, and hence the reduction technique must also retain high video fidelity.
As the MPEG video decoder market becomes more and more competitive, there is a need for high level of feature integration at the lowest possible cost to achieve success in the marketplace. One such feature that, in the past, would have required circuitry external to the video decoder function is video scaling. The kind of scaling desired is to reduce the size of the display picture by a factor, such as 2 or 4, in both the horizontal and vertical axis.
In view of the above, and in order to establish commercial advantage, a novel design is desired wherein a video scaling feature is built into the video decoder, such that advantageous use of existing decoder hardware can be applied to the processes required to produce a high quality scaled image. In one principal aspect, the present invention addresses this need.
DISCLOSURE OF THE INVENTION
Briefly summarized, this invention comprises in one aspect a video decoding system which includes a video decoder for decoding an encoded stream of video data and a decimation unit coupled to the video decoder. The video decoder produces a decoded stream of video data and the decimation unit is adapted to scale the decoded stream of video data for display. The scaling occurs within the video decode system prior to storage of the decoded stream of video data in a frame buffer.
In another aspect, the invention comprises a digital video decoding system which includes a video decoder and a video scalar. The video decoder decodes an encoded stream of video data and produces therefrom a decoded stream of video data. The video scalar is coupled to the video decoder for scaling the decoded stream of video data prior to storage thereof in a frame buffer. The video decoding system includes a normal video mode and a scaled video mode. The video scalar scales the decoded stream of video data when the digital video decoding system is in the scaled video mode. The digital video decoding system further includes display mode switch logic for switching between the normal video mode and the scaled video mode, wherein the switching occurs without perceptual degradation of the display of the decoded stream of video data.
In yet another aspect, a digital video decoding system is provided having a normal video mode and a scaled video mode. When in the normal video mode, full size frames are output for display on a video display coupled to the digital video decoding system, and when in the scaled video mode, scaled frames comprising a fractional size of the full size frames are output for display on the video display. A frame buffer is provided for temporarily storing the full size frames and the scaled frames after a decoding time thereof and prior to a display time, wherein there is a predefined latency between the decoding time and the display time. The predefined latency between the decoding time and the display time comprises a first latency when the digital video decoding system is in normal video mode and a second latency when the digital video decoding system is in scaled video mode.
In still another aspect, a frame buffer is provided for a digital video decoding system having video scaling capabilities. The frame buffer includes multiple defined memory areas for receiving I, P & B frames of a decoded stream of video data. The multiple defined memory areas comprise a first area and a second area for receiving full size I and P frames of the decoded stream of video data, as well as at least one third area for receiving scaled I, P & B frames of the decoded stream of video data commensurate with the first area and the second area receiving the full size I and P frames.
In a further aspect, the invention comprises a frame buffer for a digital video decoding system having video scaling capabilities. The frame buffer includes memory associated with the digital video decoding system. The memory is of a predefined size. The frame buffer further includes control logic for partitioning the memory of the predefined size into three buffer areas when the digital video decoding system is in a normal video mode, wherein the three buffer areas receive full size I, P & B frames of a decoded stream of video data. The control logic is further adapted to partition the memory into five buffer areas when the digital video decoding system is in a scaled video mode. The five buffer areas comprise a first area and a second area for receiving full size I and P frames of the
Campisano Francesco A.
Cheney Dennis P.
Hrusecky David A.
Ngai Chuck H.
Svec Ronald S.
Heslin Rothenberg Farley & & Mesiti P.C.
International Business Machines - Corporation
Le Vu
Radigan, Esq. Kevin P.
Steinberg, Esq. William H.
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