MPEG decoder using a shared memory

Details MPEG decoder using a shared memory MPEG decoder using a shared memory

2000-11-02

2004-01-13

Le, Vu (Department: 2613)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C375S240260, C709S213000, C710S040000, C711S151000

Reexamination Certificate

active

06678331

ABSTRACT:

TECHNICAL FIELD
The present invention relates to circuits for decompressing image sequences coded according to standard MPEG, and more specifically to a circuit including a microprocessor and an MPEG decoder that use a common memory.
BACKGROUND OF THE INVENTION
The MPEG coding standard enables storing the images of a digital image sequence in a reduced memory space. An image sequence coded according to the MPEG standard can be decoded by an MPEG decoder. An MPEG decoder can, for the decoding of an image in a sequence, use the data of the already decoded adjacent images stored in a buffer. The memory in which the coded images are stored and the buffer usually are two areas of a same memory in which the MPEG decoder can read and write. An MPEG decoder currently belongs to a circuit that further includes a microprocessor especially having the function of managing the circuit interfaces, peripherals, and internal registers. Conventionally, the microprocessor also requires for its operation the ability to read from and write into a memory.
FIG. 1
schematically shows a circuit
2
including an MPEG decoder
4
and a microprocessor
6
, respectively connected to memories
8
and
10
. Decoder
4
exchanges addresses and data with memory
8
via a bus D
1
. Decoder
4
generates a signal RW
1
for controlling memory
8
in the read or write mode. The microprocessor
6
exchanges addresses and data with memory
10
via a bus D
2
. Microprocessor
6
generates a signal RW
2
for controlling memory
10
in the read or write mode.
Such a use of two distinct memories increases the circuit cost. Thus, it has been desired to group memories
8
and
10
together in a single memory shared by the decoder and by the microprocessor.
FIG. 2
schematically shows a circuit
11
that includes an MPEG decoder
4
and a microprocessor
6
, connected to a single memory
12
by data buses D
1
and D
2
, via a control circuit
14
. Control circuit
14
, connected to receive read/write control signals RW
1
and RW
2
respectively generated by decoder
4
and microprocessor
6
, provides a read/write signal RW to memory
12
. Control circuit
14
is connected to memory
12
by a bus D.
In such a circuit, however, conflicts for access to memory
12
appear when decoder
4
and microprocessor
6
must have access to memory
12
at the same time. Control circuit
14
must thus be provided to grant priority of access to the decoder or to the microprocessor. When the decoder and the microprocessor must both perform a large number of memory accesses, and if the access priority is granted to the microprocessor, the decoder receives an insufficient number of data and it accumulates delay in the decoding. If the access priority is granted to the decoder, the microprocessor cannot operate at its maximum speed and its performances are altered. Too great a delay in the data decoding causes a circuit malfunction. For example, when the decoded data are intended for being displayed, a datum decoded too late will not be displayed on time, which will adversely affect the display quality. Thus, a conventional solution consists of granting the access priority to the decoder, while accepting a debased operation of the microprocessor.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a control circuit that limits the debasing of the microprocessor performance without causing any decoder malfunction. The control circuit grants priority to the microprocessor as long as the decoder is not delayed and, when the decoder is delayed, grants priority to the decoder until it has caught up on its delay.
The control circuit also provides means for evaluating the decoder delay.
More specifically, the circuit includes a microprocessor, an MPEG decoder for decoding an image sequence, and a memory common to the microprocessor and to the decoder, which also includes a circuit for evaluating the decoder delay, a control circuit for, if the decoder delay is greater than a predetermined level, granting the decoder the memory access priority, and otherwise, granting the microprocessor the memory access priority.
The circuit includes a clock, means for determining a reference period equal to a determined number of clock cycles, and means for determining an activity threshold. Furthermore, the circuit for evaluating the decoder delay includes means for determining during each clock cycle whether the decoder is used or unused, a counter having its content incremented each time the decoder is unused during a cycle, a subtractor, which at the beginning of each reference period subtracts the threshold from the counter content, and a comparator for checking whether the content of the counter remains negative, the output of this comparator being provided to the control circuit.
According to an embodiment of the present invention, the circuit further includes additional circuits that use the memory via the control circuit with a predetermined activity, and the control circuit is provided to alternately grant access to the memory to the additional circuits, then to the microprocessor and to the decoder. The access to the memory by the microprocessor and the decoder is controlled by the control signal generated by the evaluation circuit.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.


REFERENCES:
patent: 5212742 (1993-05-01), Normile et al.
patent: 5440752 (1995-08-01), Lentz et al.
patent: 5778096 (1998-07-01), Stearns
patent: 5793384 (1998-08-01), Okitsu
patent: 5809538 (1998-09-01), Pollmann et al.
patent: 5812789 (1998-09-01), Diaz et al.
patent: 5960464 (1999-09-01), Lam
patent: 5982360 (1999-11-01), Wu et al.
patent: 6058459 (2000-05-01), Owen et al.
patent: 0710029 (1996-05-01), None
patent: 2329985 (1999-04-01), None
Bilas et al, “Real-Time Parallel MPEG-2 Decoding in Software”, Parallel Processing Symposium, IEEE, pp. 197-203, Apr. 1997.*
Bala et al, “Experiences with Software MPEG-2 Video Decompression on an SMP PC”, Architectural and OS Support for Multimedia Applications/Flexible Communication Systems/Wireless Networks and Mobile Computing, IEEE, pp. 26-36, Aug. 1998.*
Lin et al., “On the bus arbitration for MPEG2 video decoder”, International Symposium on VLSI Technology, Systems, and Applications, IEEE, pp. 201-205, May 1995.*
Li et al., “Architecture and bus-arbitration schemes for MPEG-2 video decoder”, IEEE Trans. on Video Technology, vol. 9, iss. pp. 727-736, Aug. 1999.*
Ling et al., “A bus-monitoring model for MPEG video decoder design”, IEEE Trans. on Consumer Electronics, vol. 43, iss. 3, pp 526-530, Aug. 1997.

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