Television – Bandwidth reduction system – Data rate reduction
Patent
1994-05-18
1997-04-22
Britton, Howard W.
Television
Bandwidth reduction system
Data rate reduction
348714, H04N 726
Patent
active
056233140
ABSTRACT:
Data transfer and timing in an external DRAM memory of an MPEG decoder utilizes a repetitive pattern for synchronous writing and reading of data and data refresh including a sequence header at the beginning of a picture, a macroblock header for each of the macroblocks of a picture, and a plurality of repetitions of block decoding after each macroblock header decode.
REFERENCES:
patent: 5122875 (1992-06-01), Raychaudhuri
Grunin, Image Compression for PC Graphics, PC Magazine, vol. 11, No. 8, Apr. 28, 1992, pp. 337-350.
Leonard, Silicon Solution Merges Video, Stills, and Voice, Electronic Design, Apr. 2, 1992, pp. 45-54.
Product Hightlights, Video Compression Processor Handles Multiple Protocols, Electronic Products, Oct. 1991, pp. 85-86.
Wilson, One-Chip Video Engine, Electronic Engineering Times, Issue 659, Sep. 16, 1991, pp. 1, 8-9.
Preliminary Application Note, Using the IIT Vision Processor in JPEG Applications, Integrated Information Technology, Inc., Sep. 1991, pp. 1-15.
Preliminary Data Sheet, IIT Vision Processor--Single-Chip Microcode-Driven VSP for DCT-Based Algorithms, Integrated Information Technology, Inc., Sep. 1991, pp. 1-20.
Application Note, Video Compression Chip Set, LSI Logic Corporation, Sep. 27, 1990, pp. 1-16.
Tentative Data, ST13220 Motion Estimation Processor, SGS-Thomson Microelectronics, Jul. 1990, pp. 1-24.
Bublil Moshe
Gill Aharon
Retter Refael
Shavit Gad
Britton Howard W.
Woodward Henry K.
Zoran Microelectronics Ltd.
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