MPEG decoder frame memory interface which is reconfigurable for

Details MPEG decoder frame memory interface which is reconfigurable for MPEG decoder frame memory interface which is reconfigurable for

1996-06-14

1999-06-15

Chauhan, U.

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

345516, 348718, 395853, 711 1, G06F 1316

Patent

active

059126760

ABSTRACT:
A frame memory interface architecture which is easily adaptable to interface to any of a plurality of frame memory storage architectures. In the preferred embodiment, the present invention comprises an MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes various slave devices which access a single external memory, wherein these slave devices include reconstruction logic or motion compensation logic, a reference frame buffer, display logic, a prefetch buffer, and host bitstream logic, among others. Each of the slave devices is capable of storing or retrieving data to/from the memory according to different frame storage formats, such as a scan line format, a tiled format, and a skewed tile format, among others. The frame memory interface is easily re-configurable to each of these different formats, thus providing improved efficiency according to the present invention. The slave device then generates a request to the memory controller. In response to the request, the memory controller reads the memory transfer values stored by the slave device and sets up an address generation process based on the memory transfer values. The memory controller then generates addresses to the memory according to this address generation process to perform the memory transfer based on the memory transfer values.

REFERENCES:
patent: 5557302 (1996-09-01), Levinthal et al.
patent: 5598352 (1997-01-01), Rosenau et al.
patent: 5694585 (1997-12-01), Dwin et al.

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