Moving picture decoding circuit

Details Moving picture decoding circuit Moving picture decoding circuit

1996-02-14

1997-12-16

Au, Amelia

Television

Bandwidth reduction system

Data rate reduction

3488453, H04N 726

Patent

active

056991177

ABSTRACT:
When a macro block synchronizing signal indicating starting of processing is asserted in processing of one processing section which is formed by a macro block header and a macro block, block data of the macro block are decoded in synchronization with the assertion of MBSYNC, and next macro block header information is analyzed in continuation in the processing section. The assertion of the next MB synchronizing signal is stopped until prescribed conditions are established. Processing of the block data of the macro blocks is regularly executed from starting of one processing section, whereby utilization efficiency of operational processors is improved.

REFERENCES:
patent: 5291306 (1994-03-01), Watanabe et al.
patent: 5440345 (1995-08-01), Shimoda
patent: 5469273 (1995-11-01), Demura
patent: 5579052 (1996-11-01), Artieri
Tatsuhiko Demura et al, A Single-Chip MPEG2 Video Decoder LSI, ISSCC 94, Digest of Technical Papers, pp. 72-73, IEEE, 1994.
Querol, M., "MPEG/H261-Videodecoder MIT Wenigen Chips", Elektronik, Vo., 41, No. 23, 9 Nov. 1992, pp. 72-75.
Sun and Zdepski, "Error Concealment Strategy for Picture-Header Loss in MPEG Compressed Video", Proceedings of the Spie, vol. 2188, Feb. 1994, pp. 145-152.
European Search Report dated Apr. 11, 1997.

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