Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2011-01-25
2011-01-25
Mai, Tan V (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07877429
ABSTRACT:
FIR filter apparatus comprises an input responsive to an input signal and an FIR filter that comprises three filter stages. A first delay circuit has a first time delay coupled between two of the three filter stages. A second delay circuit has a second time delay coupled between another two of the three filter stages. The first time delay and second time delay are different.
REFERENCES:
patent: 3665171 (1972-05-01), Morrow
patent: 3703632 (1972-11-01), Shanks
patent: 4124889 (1978-11-01), Kaufman et al.
patent: 4344149 (1982-08-01), Van De Meeberg et al.
patent: 4488251 (1984-12-01), Wischermann
patent: 5050119 (1991-09-01), Lish
patent: 5118826 (1992-06-01), Cochran et al.
patent: 5119326 (1992-06-01), Cochran et al.
patent: 5212660 (1993-05-01), Orihara
patent: 5222035 (1993-06-01), Nakase et al.
patent: 5235538 (1993-08-01), Sumi et al.
patent: 5245561 (1993-09-01), Sugiyama
patent: 5333119 (1994-07-01), Raatz et al.
patent: 5388062 (1995-02-01), Knutson
patent: 5487023 (1996-01-01), Seckora
patent: 5535150 (1996-07-01), Chiang
patent: 5777910 (1998-07-01), Lu
patent: 6035312 (2000-03-01), Hasegawa
patent: 6035320 (2000-03-01), Kiriaki et al.
patent: 2002/0042802 (2002-04-01), Mogi et al.
patent: WO 99/46867 (1999-09-01), None
“An Adaptive Multiple Echo Canceller for Slowly Time Varying Echo Paths”, Yip and Etter, IEEE Transactions on Communications, Oct. 1990.
“Digital Signal Processing”, Alan V. Oppenheim et al., pp. 155-163.
“A 100 MHz Output Rate Analog-to-Digital Interface for PRML Magnetic-Disk Read Channels in 1.2 um CMOS”, Gregory T. Uehara and Paul R. Gray, ISSCC94/Session 17/Disk-Drive Electronics/Paper FA 17.3, 1994 IEEE International Solid-State Circuits Conference, pp. 280-281.
“72Mb/s PRML Disk-Drive Channel chip with an Analog Sampled Data Signal Processor”, Richard G. Yamasaki et al., ISCC94/Session 17/Disk-Drive Electronics/Paper FA 17.2, 1994 IEEE International Solid State Circuits Conference, pp. 278-279.
“A Discrete-Time Analog Signal Processor for Disk Read Channels”, Ramon Gomez et al., ISSCC93/Session 12/Hard Disk and Tape Drives/Paper FA 13.1, 1993 ISSCC Slide Supplement, pp. 162-163 and 279-280.
“A 50 MHz 70 mW 8-Tap Adaptive Equalizer/Viterbi Sequence Detector in 1.2 um CMOS”, Gregory T. Uehara et al., 1994 IEEE Custom Integrated Circuits Conference, pp. 51-54.
Mai Tan V
Marvell International Ltd.
LandOfFree
Movable tap finite impulse response filter does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Movable tap finite impulse response filter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Movable tap finite impulse response filter will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2628366