Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1998-02-11
2002-04-23
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S700000
Reexamination Certificate
active
06376906
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 9-28087 filed on Feb. 12, 1997, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a mounting structure of a semiconductor element such as a flip chip IC, which is mounted on an insulation substrate.
2. Related Arts:
FIG. 1A
shows a conventional structure of a ceramic laminated substrate
1
made of alumina (referred to as an alumina laminated substrate) and a flip chip IC
7
mounted on the alumina laminated substrate. The alumina laminated substrate
1
has via holes
2
(referred to as vias) filled with conductive material and inside wires
3
provided therein. Further, conductive lands
4
are provided on the surface of the alumina laminated substrate
1
and are connected to the vias
2
. The flip chip IC
7
has solder bumps
8
, and is joined to the alumina laminated substrate
1
by aligning the solder bumps
8
with the conductive lands
4
.
In this case, due to a difference in thermal expansion coefficient between the flip chip
7
and the substrate
1
, the larger the size of the flip chip IC
7
becomes, the larger thermal distortion of the solder bumps
8
becomes. Therefore, reinforcement resin
9
is injected into a space between the flip chip IC
7
and the substrate
1
in order to prevent the distortion of the bumps
8
. In addition, inspection lands
6
for inspecting the flip chip IC
7
are disposed on the surface of the substrate
1
and are connected to the conductive lands
4
through wiring members
5
made of conductive material as shown in FIG.
1
B.
During thermal testing of the above-mentioned mounting structure, separation of the reinforcement resin
9
from the substrate
1
started from a joining portion between an edge portion A (herebelow referred to as a fillet portion) of the reinforcement resin
9
around the flip chip
7
and the wiring members
5
. Then, the separation progressed inside of the joining portion. As a result, the reinforcement resin
9
did not sufficiently reinforce the solder bumps
8
, so that cracks were produced in the solder bumps
8
. It is assumed that the reason why the separation started from the joining portion between the fillet portion A of the reinforcement resin
9
and the wiring members
5
is because the adhesive strength between the reinforcement resin
9
and the wiring members
5
is significantly small compared to that between the reinforcement resin
9
and the alumina laminated substrate
1
.
This kind of problem is not limited to the above-mentioned mounting structure of the flip chip IC
7
, and may occur to the other mounting structures. For example, when a bare chip like a semiconductor element is mounted on an insulation substrate through wires, the wires are generally connected to bonding pads (wire lands) provided on the substrate. The semiconductor element is sealed with sealing resin. Even in this structure, a wiring pattern for connecting inspection lands and the wire lands is provided on the surface of the substrate, so that there arises a similar problem that the sealing resin is separated from the wiring pattern. Consequently, the wires are opened.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above-mentioned problems and an objective of the present invention is to provide a mounting structure of a semiconductor element mounted on an insulation substrate with resin interposed therebetween without producing separation of the resin from the substrate. More specifically, the object of the present invention is to prevent the separation of the resin from the substrate on a wiring member for an inspection land.
In a mounting structure according to the present invention, a semiconductor element is mounted on an insulation substrate through a conductive land disposed on the insulation substrate. A resin member is then disposed around the semiconductor element and the conductive land on the insulation substrate. Further, an inspection land is disposed on an outside of the resin member on the insulation substrate, and is connected to the conductive land through an inside wire provided in the insulation substrate so as to bypass the resin member. In this structure, there is no wiring pattern for the inspection land on the insulation substrate. The inside wire connecting the inspection land and the conductive land does not contact the resin member. Therefore, avoiding separating the resin member from the insulation substrate.
The semiconductor element may have a bump and can be mounted on the insulation substrate through the bump and the conductive land which are electrically connected to each other. In this case, the resin member is disposed in a space between the semiconductor element and the insulation substrate. The semiconductor element may be connected to the conductive land through a wire. In this case, the resin member covers the semiconductor element and the wire. The insulation substrate may be a laminated substrate having a via.
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patent: 5710695 (1998-01-01), Manteghi
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patent: 5891754 (1999-04-01), Bowles et al.
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Journal of Nippondenso Technical Disclosure No. 57-149.
Asai Yasutomi
Nagasaka Takashi
Ota Shinji
Chaudhuri Olik
Denso Corporation
Pillsbury & Winthrop LLP
Wille Douglas A.
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