Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2007-10-23
2007-10-23
Lee, Calvin (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C257S783000, C257S792000
Reexamination Certificate
active
11065070
ABSTRACT:
The present invention provides a mounting structure of a semiconductor chip (3) onto an insulated substrate (2). The insulated substrate (2) is made of a polyimide resin, at least side surfaces (3c) of the semiconductor chip (3) is protected by a protective resin (5) provided by a polyimide resin. The semiconductor chip (3) is held by the protective resin (5) with respect to the insulated substrate (2). Preferably, an adhesive layer (4) is provided between the semiconductor chip (3) and the insulated substrate (2). The adhesive layer (4) is also provided by a polyimide resin.
REFERENCES:
patent: 5450283 (1995-09-01), Lin et al.
patent: 5814894 (1998-09-01), Igarashi et al.
patent: 5821320 (1998-10-01), Maeda et al.
patent: 5864178 (1999-01-01), Yamada et al.
patent: 5937320 (1999-08-01), Andricacos et al.
patent: 10-107086 (1998-04-01), None
patent: 10-199936 (1998-07-01), None
patent: 11-026652 (1999-01-01), None
patent: 11-220077 (1999-08-01), None
patent: 2001-060641 (2001-03-01), None
English language Abstracts of JP 10-107086 and 2001-060641.
Copy of Japanese Office Action dated Jun. 27, 2006 citing the above references.
Article entitled “Electronic Packaging And Interconnection Handbook” by Charles A. Harper, published in Technology Seminars, Inc., Lutherville, Maryland, ISBN 0-07-026684-0, 1991.
Bednarek Michael
Lee Calvin
Paul Hastings Janofsky & Walker LLP
Rohm & Co., Ltd.
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