Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
1999-04-06
2001-12-04
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S115000, C438S106000, C438S110000
Reexamination Certificate
active
06326239
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon Japanese Patent Applications No. Hei. 10-94874 filed Apr. 7, 1998, No. Hei. 10-305507 filed Oct. 27, 1998, and No. Hei. 11-43801 filed Feb. 22, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention related to a mounting structure and a mounting method of an electronic part such as a semiconductor element, a chip type capacitance or a resistor, which is electrically connected to a mounting substrate via electrodes.
2. Related Arts
In one conventional mounting structure for an electric circuit device such as a HIC (Hybrid Integrated Circuit), when surface mounting electronic part is mounted on a substrate, a conductive adhesive such as Ag (silver) paste is used to mount them for the purpose of Pb(lead)-free or fleon-free (elimination of a washing process for washing flux remains).
FIG. 15
shows the above-mentioned conventional mounting structure. In this figure, a laminated ceramic capacitor
42
for surface mounting, which has a pair of electrodes
43
, is mounted on a mounting substrate
41
made by an insulating material such as ceramic or resin. This mounting structure is obtained by following process. That is, the laminated ceramic capacitor
42
is mounted on the mounting substrate
41
. The Ag paste
44
is transcribed on the pair of electrodes
43
of the mounting substrate
41
by a screen printing. The laminated ceramic capacitor
42
is mounted on the Ag paste
44
with a predetermined load and time condition. Then Ag paste is hardened.
According to a thermal cycle test (from −40° C. to 150° C., 1000 cycles) on the above-described conventional mounting structure, it is found that cracks are generated in some interfaces, and that junctions of the interfaces may be deteriorated by the cracks. Here, the interfaces include the one between electrodes
42
a
of the laminated ceramic capacitor
42
and the Ag paste
44
, and between the electrodes
43
of the mounting substrate
41
and the Ag paste
44
. These cracks may occur in the following manner.
In a mounting structure using a reflow soldering, flux components remove dirt such as oxide compounds or organic matters on the electrodes of the electronic part and the electrodes of the mounting substrate, and the solder and electrode materials are metallically bonded each other due to a reflow heating. Hence, a dependency of a bonded state against the electrode materials is rather small.
On the other hand, in the mounting structure using Ag paste
44
, Ag fillers, which exist in the Ag paste
44
independently, are connected in chains each other and are connected to each electrode
42
a
,
43
in proportion to hardening and contraction of a binder resin in the Ag paste
44
.
Therefore, the bonded state is likely to be affected by the electrode material (specifically surface material), and an adhesive strength between each of the electrodes
42
a
,
43
and the Ag paste becomes small compared to that of soldering.
According to investigation to check where the cracks are generated in the Ag paste
44
in the thermal cycle test, it is found that the cracks are generated mainly at peripheral portion of bonded portions between Ag paste
44
and the electrodes
42
a
,
43
. That is, the cracks are generated at bonded portions where the adhesive strength becomes small due to heating contractions of Ag paste
44
under high temperature.
In another conventional mounting structure, an electronic part having a narrow pitch land (electrode) such as a semiconductor element is mounted on a mounting substrate by a flip chip mounting by using a solder. This mounting structure is obtained by following steps shown in
FIGS. 16A-16D
.
As shown in
FIG. 16A
, a mounting substrate
52
having electrodes (electrodes or lands)
51
is provided. As shown in
FIG. 16B
, solder pastes
53
are printed on the mounting substrate
52
. Here, a diameter of each solder pastes
53
is substantially equal to that of land
51
to obtain desired bonded lifetime of the solder. As shown in
FIG. 16C
, a semiconductor element having solder bumps
54
is aligned and mounted on the mounting substrate. The solder bumps
54
and the solder pastes
53
are bonded by melting each other by a reflow process. Then, the semiconductor element
55
is electrically connected to the mounting substrate
52
, as shown in FIG.
16
D.
In this conventional mounting structure, one of a pattern tolerance of the lands
51
, a printing displacement of the solder paste
53
, and a mounting displacement of the semiconductor element relative to the mounting substrate may occur. Hence, the lands
51
and the solder paste
55
may be displaced each other. However, the solder paste
53
and the solder bump
54
are melted, and spread on the lands
53
, then the melted solder will return to the lands
51
. The solder pastes
53
need to contact at more than half area with the lands
51
to have the melted solder return to the lands
51
completely. On the other hand, when the solder pastes
53
contact the lands
51
at less than half area, the melted solder may not return to the lands
51
completely. In such a case, the melted solder may remain on the mounting substrate as a solder ball, or be merged with the adjacent solder at the adjacent land
51
, then the adjacent lands
51
may be short-circuit by the melted solder as shown in FIG.
17
.
Consequently, reliability of electrical connection of the semiconductor element or the electronic part may decrease due to the decreasing of an amount of the solder of lands
51
or short-circuit between adjacent lands
51
.
Recently, a land pitch of the semiconductor element
55
is desired to be less than 300 &mgr;m for the purpose of fining. When the ceramic laminated substrate is employed as the mounting substrate
52
, the pattern accuracy may be decreased due to non-uniformity of baking contraction, and a size tolerance of around 1% will be generated. Therefore, the following accuracy is severely required to satisfy this desire. Here, the accuracy includes a pattern accuracy of the land
51
provided on the mounting substrate
52
, a printing alignment of the solder pastes
53
, accuracy of weight of each solder paste, and a mounting accuracy of the semiconductor element
55
to the mounting substrate
52
.
However, when the semiconductor element has a size of 10 mm×10 mm, at a peripheral portion of the semiconductor element
55
, the pattern tolerance may be 0.07 mm, the printing displacement may be 0.05 mm, and the mounting displacement may be 0.03 mm. In this case, the displacement between the solder paste
53
and the solder bump
54
with respect to the land
51
is estimated to be around 0.13 mm by calculating root mean square of each displacement. When the land pitch is set to be less than this estimated value, adjacent solders may be merged to short-circuit.
However, since the size of land
51
is determined based on the bonded lifetime or predetermined displacements, the land pitch can not be set to be less than 0.28 mm when the land size is set to 0.15 mm.
SUMMARY OF THE INVENTION
The present inventions are made in view of the above-mentioned inconvenience of the conventional mounting structures.
The present invention is based on the finding that a conductive adhesive such as Ag paste has a high adhesive strength when it is bonded with a ceramic or an insulating material, compared to that when the Ag paste is bonded with a metal. Here, the ceramic is used for a body member of a bonding substrate or a laminated ceramic capacitor (e.g. alumina). The insulating material is used for a mounting substrate (e.g. resin or ceramic).
A first object of the present invention is to provide a mounting structure or a mounting method of an electronic part, which can prevent cracks from generation in a conductive adhesive, when the electronic part, which has a body member formed by an insulating material and electrodes exposed to a surface of the body member, is mounted on electrod
Asai Yasutomi
Imai Hirokazu
Nagasaka Takashi
Ootani Yuji
Bowers Charles
Denso Corporation
Pillsbury & Winthrop LLP
Schillinger Laura
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