Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-02-26
2004-04-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S099000, C257S100000, C257S666000
Reexamination Certificate
active
06717256
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device, and more specifically to a semiconductor device having a light emitting capability and/or a light receiving capability. Further, the present invention relates to a circuit substrate for supporting such a semiconductor device as the above. Still further, the present invention relates to a combination of the semiconductor device and a storage receptacle for collectively holding a plurality of the semiconductor devices.
BACKGROUND ART
FIG.
20
and
FIG. 21
show a prior art semiconductor device. This semiconductor device X is a light emitting diode (LED), and includes a first lead
100
, a second lead
200
, a semiconductor chip
300
as a light emitting element, a connecting wire W, and a protective package
400
.
The semiconductor chip
300
is placed at an inner end
100
a
of the first lead
100
. The semiconductor chip
300
has an upper surface
330
electrically connected with an inner end
200
a
of the second lead
200
via a wire W. The protective package
400
is made of a transparent resin such as an epoxy resin, and completely covers the semiconductor chip
300
and the connecting wire W. Further, the protective package
400
partially covers the first and the second leads
100
,
200
. In
FIGS. 20 and 21
, the inner portion of the first lead
100
covered by the protective package
400
is indicated by numeral code
110
whereas the outer portion of the first lead
100
extending out of the protective package
400
is indicated by numeral code
111
. Like the first lead
100
, the second lead
200
also has an inner portion
220
covered by the protective package
400
and an outer portion
221
extending out of the protective package
400
.
As shown in
FIG. 21
, the inner portion
110
of the first lead
100
extends straightly whereas the outer portion
111
is bent. The outer portion
111
of the first lead
100
has a free end
111
a
flush with a bottom surface of the protective package
400
. The second lead also has the same constitution as the first lead, and thus has a free end
221
a
flush with the bottom surface of the protective package
400
.
The circuit substrate
5
is provided with pads
52
a
,
52
b
for establishing electrical connection with the semiconductor device X. The semiconductor device X is mounted on the circuit substrate
5
, with the free ends
111
a
,
221
a
connected with the pads
52
a
52
b
respectively.
The prior art semiconductor device X is inconvenient in the following points: Specifically, the semiconductor device X is mounted on the circuit substrate
5
via the leads
100
,
200
which are bent as described above. In such a case, as shown in
FIG. 21
, the entire protective package
400
of the semiconductor device X comes above the circuit substrate
5
. This leads to a problem that a dimension Dh between a top Ap of the semiconductor device X and an upper surface of the circuit substrate
5
becomes large.
DISCLOSURE OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device capable of solving or at least reduce the problem described above.
Another object of the present invention is to provide a circuit substrate for mounting such a semiconductor device as the above.
Still another object of the present invention is to provide a combination of a plurality of the semiconductor devices and a storage receptacle for collectively holding these semiconductor devices.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip; a protective package covering the semiconductor chip; a first lead conducting to the semiconductor chip, including an inner portion covered by the protective package and at least one outer portion extending out of the protective package; a second lead conducting to the semiconductor chip, including an inner portion covered by the protective package and at least one outer portion extending out of the protective package; wherein each of the outer portions of the first lead and the second lead is flat.
Preferably, the outer portion of the first lead and the outer portion of the second lead extend in a same plane.
Further, the inner portion and the outer portion of the first lead, and the inner portion and the outer portion of the second lead may extend in a same plane.
According to a preferred embodiment of the present invention, each of the first lead and the second lead has a plurality of outer portions extending out of the protective package, and the outer portions extend in a same plane.
Preferably, the protective package includes at least a pair of opposed side surfaces, and each of the side surfaces has a first slanted portion and a second slanted portion.
The first slanted portion and the second slanted portion may be flat and meet with each other at a predetermined angle.
The semiconductor chip is a light emitting element for example. Also, the semiconductor chip is a light receiving element for example.
According to another preferred embodiment of the present invention, the semiconductor device further comprises an additional semiconductor chip, a third lead conducting to the additional semiconductor chip, and a fourth lead conducting to the additional semiconductor chip. The third lead includes an inner portion covered by the protective package and a flat outer portion extending out of the protective package, and the fourth lead includes an inner portion covered by the protective package and a flat outer portion extending out of the protective package.
According to a second aspect of the present invention, there is provided a circuit substrate for mounting a semiconductor device including a protective package and flat leads extending out of the protective package. The substrate comprises: a main surface formed with a predetermined wiring pattern; a plurality of connecting pads formed in the main surface for conduction to the leads of the semiconductor device; and a through hole corresponding to a shape of the protective package.
Preferably, the connecting pads are disposed around the through hole.
Preferably, the main surface mounted with the semiconductor device is laminated with a coating member.
According to a third aspect of the present invention, a combination of a plurality of semiconductor devices and a storage receptacle for storing the same is provided: each of these semiconductor devices includes an upper surface having a predetermined function, and a bottom surface away from the upper surface, whereas the storage receptacle includes a carrier member having a plurality of recesses opening upward, and a covering tape having an adhesive surface attached to the carrier member, and the semiconductor device is housed in the recess with the bottom surface facing upward.
According to a preferred embodiment of the present invention, the upper surface of the semiconductor device is formed with a light-condensing portion.
Preferably, each of the recesses includes a larger space and a smaller space.
Preferably, the recesses are formed longitudinally of the carrier member at a predetermined interval.
REFERENCES:
patent: 5198888 (1993-03-01), Sugano et al.
patent: 5495125 (1996-02-01), Uemura
patent: 48-93284 (1973-12-01), None
patent: 59-195757 (1984-12-01), None
patent: 62-131441 (1987-08-01), None
patent: 63-168931 (1988-11-01), None
patent: 63-173721 (1988-11-01), None
patent: 01-120875 (1989-05-01), None
patent: 2-101559 (1990-08-01), None
patent: 4-5652 (1992-01-01), None
patent: 05-319403 (1993-12-01), None
patent: 06-296045 (1994-10-01), None
patent: 08-032106 (1996-02-01), None
English language Abstract of Japanese Pat.Pub.Nos. 06-296045 dated Oct. 21, 1994, 08-032106 dated Feb. 2, 1996, 05-319403 dated Dec. 3, 1993, and 01-120875 dated May 12, 1989.
Copy of English Translation of International Search Report;. Copy of International Preliminary Examining Report.
Sano Masashi
Suzuki Nobuaki
Suzuki Shin'ichi
Andújar Leonardo
Bednarek Michael D.
Flynn Nathan J.
Rohm & Co., Ltd.
Shaw Pittman LLP
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