Electricity: motive power systems – Switched reluctance motor commutation control
Reexamination Certificate
2003-01-27
2004-07-13
Leykin, Rita (Department: 2837)
Electricity: motive power systems
Switched reluctance motor commutation control
C318S132000, C318S434000, C361S018000, C327S561000, C327S562000
Reexamination Certificate
active
06762576
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a motor driving device which is mainly formed of a semiconductor integrated circuit and supplies a driving current to drive a three-phase motor.
2. Description of Related Art
Output transistors supplying current to stator coils at high voltage and high electric power are placed at an output stage in a semiconductor integrated circuit so as to drive a three-phase motor. Each of these output transistors is frequently formed of an n-channel metal-oxide semiconductor field effect transistor (nMOSFET, hereinafter called n-channel transistor). The reason is that the on-state resistance per a unit area in a p-channel MOSFET (pMOSFET, hereinafter called p-channel transistor) is larger than that in the n-channel transistor. Therefore, when the output transistors are formed of p-channel transistors respectively, the manufacturing cost of a motor driving device having the output transistors is heightened.
FIG. 3
is a circuit view showing the configuration of a conventional motor driving device. In
FIG. 3
,
31
u
,
31
v
and
31
w
indicate three stator coils of a three-phase motor connected with each other in a Y shape.
1
indicates a direct voltage source.
2
indicates a high voltage source.
3
indicates the ground.
4
and
5
indicate a pair of n-channel output transistors. A driving current passes through the two stator coils and the n-channel output transistor
4
or
5
to drive the three-phase motor.
6
indicates a p-channel transistor used to drive the n-channel output transistor
4
.
7
indicates an n-channel transistor used to drive the n-channel output transistor
4
.
8
indicates an inverter for inverting a driving pulse A to input the inverted driving pulse A to gates of the transistors
6
and
7
.
9
and
10
indicate two inverters serially connected with each other, and a driving pulse B is inverted twice in the inverters
9
and
10
.
21
and
22
indicate two Zener diodes serially connected with each other in opposite directions. A voltage clamp circuit is formed of the Zener diodes
21
and
22
.
A source of the p-channel transistor
6
is connected to the high voltage source
2
, a drain of the p-channel transistor
6
is connected to a gate of the n-channel output transistor
4
, and a gate of the p-channel transistor
6
is connected to an output terminal of the inverter
8
. A drain of the n-channel transistor
7
is connected to the gate of the n-channel output transistor
4
, a source of the n-channel transistor
7
is connected to the ground
3
, and a gate of the n-channel transistor
7
is connected to the output terminal of the inverter
8
.
A drain of the n-channel output transistor
4
is connected to the direct voltage source
1
, and a source of the n-channel output transistor
4
is connected to a terminal W of the stator coil
31
w
. A drain of the n-channel output transistor
5
is connected to the terminal W of the stator coil
31
w
, a source of the n-channel output transistor
5
is connected to the ground
3
, and a gate of the n-channel output transistor
5
is connected to an output terminal of the inverter
9
. The driving pulse B is inverted in the inverter
10
and the inverter
9
in that order and is applied to the gate of the n-channel output transistor
5
.
Also, the voltage clamp circuit composed of the Zener diodes
21
and
22
is placed to connect the gate and the source of the n-channel output transistor
4
. The voltage clamp circuit is used to protect the n-channel output transistor
4
from an excess positive voltage and an excess negative voltage applied to the gate of the n-channel output transistor
4
.
Also, a motor driving device having the same configuration as that of the motor driving device shown in
FIG. 3
is connected to each of terminals U and V of the stator coils
31
u
and
31
v.
Next, an operation of the motor driving device connected to the terminal W of the stator coil
31
w
will be described below.
FIG. 4
is a time chart of the driving pulses A and B input to the inverters
8
and
10
respectively, and each of
FIG. 5A
, FIG.
5
B and
FIG. 5C
is an explanatory view showing an operation of the motor driving device.
As shown in
FIG. 4
, a timing of inputting the driving pulse A to the inverter
8
differs from a timing of inputting the driving pulse B to the inverter
10
. As shown in
FIG. 5A
, when the driving pulse A is set to a high level, the driving pulse B is set to a low level. In this case, the gates of the transistors
6
and
7
are set to a low level due to the driving pulse A inverted in the inverter
8
, the p-channel transistor
6
is turned on, and the n-channel transistor
7
is turned off. Thereafter, the gate of the n-channel output transistor
4
is set to a high level, and the n-channel output transistor
4
is turned on. Also, the gate of the n-channel output transistor
5
is set to a low level due to the driving pulse B inverted twice in the inverters
9
and
10
, and the n-channel output transistor
5
is turned off. Therefore, in a first operation, a driving current is supplied from the direct voltage source
1
to the stator coils
31
w
and
31
v
through the n-channel output transistor
4
to drive the three-phase motor.
Also, as shown in
FIG. 5B
, when the driving pulse B is set to a high level, the driving pulse A is set to a low level. In this case, the gates of the transistors
6
and
7
are set to a high level due to the driving pulse A inverted in the inverter
8
, the p-channel transistor
6
is turned off, the n-channel transistor
7
is turned on, the gate of the n-channel output transistor
4
is set to a low level, and the n-channel output transistor
4
is turned off. Also, the gate of the n-channel output transistor
5
is set to a high level due to the driving pulse B inverted twice in the inverters
9
and
10
, and the n-channel output transistor
5
is turned on. Also, the direct voltage source
1
is connected to the terminal U of the stator coil
31
u
due to the operation of the motor driving device connected to the terminal U. Therefore, in a second operation, a driving current supplied from the direct voltage source
1
flows through the stator coils
31
u
and
31
w
and goes to the ground
3
through the n-channel output transistor
5
to drive the three-phase motor.
In cases where the three-phase motor is driven, the driving pulses A and B are set to the low level together in a stop time period other than the active time period of the output transistor
4
or
5
shown in
FIG. 5A
or FIG.
5
B. In this stop time period, as shown in
FIG. 5C
, both the n-channel output transistors
4
and
5
are set to the off-state together, no current passes through the stator coil
31
w
, and the motor driving device is set to a high impedance when the motor driving device placed at the output stage of the semiconductor integrated circuit is seen from the stator coil
31
w
. In this case, when the n-channel output transistor
4
or
5
is set to the off-state during the stop time period after the first or second operation shown in
FIG. 5A
or
FIG. 5B
, charge supplied from the direct voltage source
1
remains in the stator coil
31
w
, and the terminal W is set to a high voltage due to the remaining charge. Therefore, in cases where a voltage higher than a withstand voltage between the gate and the source of the n-channel output transistor
4
is supplied from the direct voltage source
1
to the stator coil
31
w
, it is required to protect the n-channel output transistor
4
from the excess voltage applied between the gate and the source of the n-channel output transistor
4
and to prevent the gate of the n-channel output transistor
4
from being damaged.
To protect the n-channel output transistor
4
, the voltage clamp circuit composed of the Zener diodes
21
and
22
is placed to connect the gate and the source of the n-channel output transistor
4
. In a third operation, as shown in
FIG. 5C
, the voltage clamp circuit composed of the Zener diodes
21
and
Miyazaki Katsumi
Suetsugu Daisuke
Sugata Yuka
Burns Doane Swecker & Mathis L.L.P.
Leykin Rita
Renesas Technology Corp.
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