Electricity: motive power systems – Switched reluctance motor commutation control
Reexamination Certificate
2003-04-22
2004-06-08
Masih, Karen (Department: 2837)
Electricity: motive power systems
Switched reluctance motor commutation control
C318S569000, C318S567000
Reexamination Certificate
active
06747426
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an apparatus and method for controlling a motor. More particularly, the invention relates to control of a motor having a motor driver for driving the motor in accordance with an input of digital-format drive data of a predetermined length.
More specifically, the present invention relates to a motor control apparatus and method in which a portion of motor drive data, which is generated by a motor controller of a printing apparatus or the like, is replaced with other data in an arrangement in which the motor drive data is acquired from a memory by DMA (Direct Memory Access).
BACKGROUND OF THE INVENTION
Printers are becoming increasingly popular and great strides are being made in printing techniques as well. Printers are adapted so as to print images on paper based upon image information. A printing method of much interest employed in such printers is the ink-jet printing method, which is method is a method of performing printing by ejecting ink onto paper from a printhead. This method is advantageous in that a highly precise image can be printed at high speed and is superior to other printing methods in terms of running cost and quietness.
In an ink-jet printer that employs the ink-jet printing method, generally stepping motors are used for paper-feed, carriage movement and recovery operations. Recently, there has been an increase in arrangements in which control of these motors is carried out not by a CPU but by a motor control circuit provided within a special-purpose system LSI (referred to as an “ASIC” below) chip that controls the overall printer.
The reason for this is that owing to the more complicated stopping control that accompanies an increase in printer resolution and in order to lower machine noise, there has been an increase in arrangements in which the motor excitation method is W1-2 phase excitation and 2W1-2 phase excitation and drive is by microsteps. Further, owing to an increase in the printing speed of these printers, motor driving speed also is higher than heretofore. As a consequence, the timing at which phase excitation switching takes places speeds up and therefore the burden upon the CPU increases. With conventional sequence control, therefore, situations arise in which the system cannot keep up with the higher switching speed.
Accordingly, an arrangement has been adopted in which a special-purpose hardware circuit for motor control is provided within an ASIC, data in a drive table stored on a ROM (Read-Only Memory) is expanded in a RAM, this data is incorporated in the special-purpose hardware for motor control by DMA transfer, and the data is transmitted to a motor driver to control the motor without the intermediary of a CPU.
For example, the specifications of Japanese Patent Application Laid-Open Nos. 2001-286190 and 2001-286189 (these two applications correspond to U.S. Patent Publication No. 2001/045806 A1) disclose a method in which data of a motor drive table that has been stored in a RAM is incorporated in a motor driver controller successively by DMA transfer without the intermediary of a CPU, thereby controlling a motor driver and alleviating the load on a CPU.
A conventional motor control method using DMA transfer will be described in detail with reference to the drawings.
FIG. 2
is a block diagram illustrating a prior-art arrangement for performing motor control using DMA transfer. An arrangement in which drive data is transferred to a motor driver serially will be taken as an example.
As shown in
FIG. 2
, this control arrangement includes a RAM
1
, a printer controller LSI (ASIC) chip
2
, a motor driver
3
, a CPU
4
and a ROM
5
. Various functional blocks for controlling printer operation are incorporated within the printer controller LSI
2
. Mainly the portions relating to motor drive are illustrated. A DMA controller
6
performs DMA transfer with respect to the RAM
1
based upon a RAM access request of each functional block. Motor drive data that has been stored in a ROM
5
also is developed in the RAM
1
via the DMA controller
6
within the ASIC
2
.
A motor driver controller
7
includes a control block
8
, a data controller
9
, a serial data generator
12
and a timing controller
13
. The control block
8
is provided with a control register for driving the motor drive controller. On the basis of the content of the control register, the control block
8
executes sequential control of the functions within the motor drive controller. The writing of data to the control register is performed by the CPU. The data controller
9
requests the DMA controller
6
for transfer of DMA data from a designated address of the RAM
1
. Reference numerals
10
and
11
denote data that the data controller
9
has acquired and latched. The data
10
is motor driver control data, and the data
11
is time data. A serial data converter
12
converts the latched drive data from a parallel signal to serial data, which is synchronized to a transfer clock, by a shift register. A timing controller
13
manages excitation time based upon the latched time data.
FIG. 3
is a diagram illustrating an example of transfer timing for transfer of drive data to the motor driver.
FIG. 3
illustrates the timing of the strobe signal
14
, transfer clock
15
and drive data
16
transmitted to the motor driver
3
from the printer controller LSI
2
, which includes the motor driver controller
7
of
FIG. 2
, as well as the internal structure of the motor driver
3
.
The drive data
16
is stored successively in a shift register
17
within the motor driver
3
in sync with the transfer clock
15
. The data is latched in a latch
18
by the strobe signal
14
. The output of the motor driver is finalized, after the data is latched within the latch
18
, at the rising edge of the strobe signal
14
. That is, excitation time is managed at the intervals at which the strobe signal
14
is generated. More specifically, the latched data is partitioned into bits on a per-control-element basis and is used in control of each drive control block.
A torque data controller
19
is for changing over the levels of the currents of A and B phases while maintaining the set values of the currents of these two phases. As a result, the current applied to the motor can be set stepwise in a state in which the setting of the ratio of the currents of the A and B phases is the same. This makes it possible to set torque. Reference numerals
20
,
21
and
22
denote control blocks on the side of the A phase, in which block
20
controls the flow of regenerative current (decay mode), block
21
the current value and block
22
the phase with respect to the A-phase output current. Reference numerals
23
,
24
and
25
denote control blocks on the side of the B phase. Control relating to these blocks is similar to that of the blocks on the A-phase side.
In the above-described example of the prior art, however, data of the motor drive table that has been expanded in the RAM is incorporated in the motor driver controller by DMA transfer. The motor driver controller transfers this data to the motor driver at the set excitation time intervals. Specifically, the data of the drive table that has been stored in the RAM is transferred to the motor driver as is. As a result, in a case where it is desired to change only certain specific information such as torque setting bits, it is necessary to rewrite the specific bits, which are desired to be changed in the drive table within the RAM, by a CPU in one-byte or two-byte (=one word) units, or to store these specific bits in another area of the RAM as data of another motor drive table.
If it is so arranged that the specific bit of the drive table is rewritten by the CPU, the CPU is occupied for the period of time required for the rewriting of the drive table data. During this time the CPU cannot execute other tasks and, hence, there is the possibility that the overall performance of the printer will decline. On the other hand, assume that the arrangement is such that the data of another m
Horiuchi Akinori
Katsu Takuji
Kuronuma Akira
Nakayama Toru
Tanaka Souhei
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