Electricity: motive power systems – Positional servo systems – Program- or pattern-controlled systems
Reexamination Certificate
2001-03-27
2003-05-13
Leykin, Rita (Department: 2837)
Electricity: motive power systems
Positional servo systems
Program- or pattern-controlled systems
C318S625000, C318S696000
Reexamination Certificate
active
06563282
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a motor control apparatus, in particular, a motor control apparatus to drive-control a motor controlled by combination of a plurality of phase signals.
2. Related Background Art
Conventionally, as a power source to convey paper sheet or the like for a printer, etc., and as driving means for such a sheet delivery mechanism or the like, a motor (stepping motor) controlled by a combination of phase signals is being used.
FIG. 13
is to show a configuration of a motor control portion to control a motor as described above in a conventional image-forming apparatus or the like. In
FIG. 13
, in which reference numeral
2001
denotes a CPU to control a series of operations while reference numeral
2002
denotes a system bus, respective configuring members are brought into connection to this system bus. Reference numeral
2003
denotes a ROM of the CPU, where a program and respective kinds of data are stored.
Reference numeral
2004
denotes a data RAM, reference numeral
2005
denotes a timer IC, reference numeral
2006
denotes an interrupt signal from the timer IC, reference numeral
2007
denotes phase pattern signals to operate the motor, reference numeral
2008
denotes a buffer circuit to interface the motor with the CPU, and reference numeral
2009
denotes the motor.
The CPU
2001
receives the interruption from the timer IC in every constant time to control the phase pattern signals of the motor
2009
via a bus interface circuit or a buffer circuit configured by an amplifier based on the drive data expanded in the ROM
2003
or the RAM
2004
. That is, the CPU
2001
reads out the drive data and transfers them to the buffer circuit
2008
.
FIG. 14
shows operation timing of the motor in FIG.
13
. Here, the motor
2009
is to operate in combination of two phase signals of the signal A and the signal B, and combination of the respective signal levels is changed to give the states of T1 to T4 to give rise to a predetermined angular rotation. (Subsequently, T4 goes back to T1)
FIG. 15
is to show how acceleration as well as constant speed rotation is executed on the motor controlled by conventional configuration in
FIG. 13
or the like.
FIG. 15
shows velocity and time in a motor in a graph, wherein, as shown in the drawing, phase switching is executed at the points of time t1, t2 or the like so that control is changed gradually from a slow velocity to a fast velocity, and is controlled at a constant velocity at the time point of the reference numeral
4001
. Generally, this kind of motor requires a high torque at the time when rotation starts, and therefore it is required to start the operation at a low velocity and change it gradually to a high velocity operation.
Incidentally, as concerns the velocity of the motor, as shown in
FIG. 14
, the rotational angle due to change in the state of the phase signal is constant, thereby the period of the phase signal given to the motor is shortened so that the motor is rapidly switched from T1 to T2, T3, and T4 to consequently rotate at a higher speed.
The bottom part in
FIG. 15
is to show an example of velocity control of the motor by phase switching, and an operation such as to switch the phase signal of the motor from T1 to T2 in
FIG. 3
at a certain time point t1 and switch it from T2 to T3 at a time point t2 repeatedly to make the time until the respective phase signals is switched gradually shorter.
Here, the motor velocity control method in a conventional system will be described with reference to
FIG. 13
again.
The CPU
2001
in
FIG. 13
prepares the velocity table on the RAM
2004
(or ROM
2003
) to operate the motor
2009
by instruction of the not shown operation panel or the like. In addition, the phase signal to be supplied to the motor gives the output signal of the CPU or T1 pattern to the motor
2009
via the buffer circuit
2008
.
In addition, the operation start order is given to the timer
2005
to set the initial value of the drive data table. Thereafter, the operation of the timer
2005
gives rise to interruption
2006
for the CPU
2001
, then the CPU
2001
in receipt of this interruption rewrites the phase signal to the motor
2007
as T2 to read out the next table value from the RAM
2004
to set it into the timer
2005
. This operation is repeated sequentially so as to stop renewing the timer at the time when the speed has reached a predetermined one and to proceed with a constant speed operation by only renewing the phase signal pattern thereafter. The operation stipulated so far, the operation in
FIG. 15
is realized.
However, in the above described prior art configuration, based on interruption from the timer IC the phase signal is switched lead by the CPU, giving rise to the following problems.
1) Time Delay of Switching Timing of Phase Signal
Time delay from interruption to setting of the signal takes place, giving rise to an inconvenience of dispersion in rotation velocity in general except such a case that the phase switching time is not problematic since it is sufficiently large compared with the interruption processing time.
2) Decrease in Processing Velocity of CPU Due to Interruption
In the case where there exists a plurality of motors and the rotation velocity of the motor is fast, the interval of interruption to be inputted to the CPU becomes short, giving rise to an inconvenience that the other processing efficiency of the CPU gets worse.
3) Increase in Table Memory
In a system where a plurality of acceleration-deceleration characteristics of a motor are required, the values of the table increase, giving rise to cost-up.
SUMMARY OF THE INVENTION
The present invention has been made in view of the points described so far, and the object thereof is to provide a motor control apparatus capable of reducing load of a CPU being control means and of operation at a high speed by simple and inexpensive configuration.
In addition, the present invention can be embodied simply and inexpensively in the motor control apparatus, can reduce load of the CPU being control means, and an object hereof is to enable the memory capacity to store the motor drive data table to be reduced.
That is, according to the present invention, in a motor control apparatus to drive-control a motor to be controlled in combination of a plurality of phase signals, comprising:
a velocity table memory storing velocity data for setting velocity of the above described motor step by step;
a memory access control portion to sequentially read out data of said velocity table without being intermediated by control of a CPU controlling the entire drive control of the motor;
time conversion means to convert data value read out from the above described velocity table to time data; and
a phase signal generating portion to generate phase switching signals to operate the above described motor based on an output of the above described time conversion means,
wherein such a configuration has been adopted in that with time data output signals of said the above described time conversion means, occurrence of access to a next memory table toward the above described memory access control portion is urged.
In addition, according to the present invention, in a motor control apparatus to drive-control a motor to be controlled in combination of a plurality of phase signals, a configuration has been adopted so as to comprise:
a velocity table memory storing velocity data for setting velocity of the above described motor step by step;
a memory access control portion to sequentially read out data of said velocity table without being intermediated by control of a CPU controlling the entire drive control of the motor;
time conversion means to convert data value read out from the above described velocity table to time data;
a phase signal generating portion to generate phase switching signals to operate the above described motor based on an output of the above described time conversion means; and
interval control means to urge the above described memory access control port
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Leykin Rita
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