Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1997-12-23
2001-03-06
Britton, Howard (Department: 2713)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C375S240160
Reexamination Certificate
active
06198772
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to apparatus for encoding digital visual images, including spatial (Intra-picture) and temporal (inter-picture) compression, that is redundancy within a picture and redundancy between pictures. Redundancy within pictures is reduced, or even eliminated, by the use of the discrete cosine transform, quantization, and variable length encoding. Redundancy between pictures is reduced, or even eliminated, through the use of motion vectors. Specifically, the invention relates to an encoder, as a scalable encoder system, having a motion estimation processor (MEPROC). That is, a scalable architecture MPEG-2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a motion estimation processor (MEPROC), reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.
BACKGROUND OF THE INVENTION
Within the past decade, the advent of world-wide electronic communications systems has enhanced the way in which people can send and receive information. In particular, the capabilities of real-time video and audio systems have greatly improved in recent years. In order to provide services such as video-on-demand and videoconferencing to subscribers, an enormous amount of network bandwidth is required. In fact, network bandwidth is often the main inhibitor to the effectiveness of such systems.
In order to overcome the constraints imposed by networks, compression systems have emerged. These systems reduce the amount of video and audio data which must be transmitted by removing redundancy in the picture sequence. At the receiving end, the picture sequence is uncompressed and may be displayed in real-time.
One example of an emerging video compression standard is the Moving Picture Experts Group (“MPEG-2”) standard. Within the MPEG-2 standard, video compression is defined both within a given picture and between pictures. Video compression within a picture is accomplished by conversion of the digital image from the time domain to the frequency domain by a discrete cosine transform, quantization, and variable length coding, such as Huffman coding. Video compression between pictures is accomplished via a process referred to as motion estimation and compensation, in which a motion vector plus difference data is used to describe the translation of a set of picture elements (pels) from one picture to another.
The ISO MPEG-2 standard specifies only the syntax of bitstream and semantics of the decoding process. The choice of coding parameters and trade-offs in performance versus complexity is left to the encoder developers. Since MPEG-2 encoder development is complex and expensive, an encoder solution that is flexible for different applications and that can expand as the customer's needs evolve, that is, a scalable encoder, is desirable.
One computation intensive aspect of MPEG-2 encoding is motion estimation and compensation. This involves such computation intensive steps as memory fetches and stores, searches, comparisons, matches, and motion vector calculations. A need exists for a fast search for a best-match macroblock in a search window on downsampled full pixel values.
A further need exists for a fast search on non-downsampled reconstructed data around the best match macroblock to find a more precise match to use for motion vector coding.
OBJECTS OF THE INVENTION
It is a primary object of the invention to provide a fast search for a best-match macroblock in a search window on downsampled full pixel values.
It is a further object of the invention to provide a processor for a fast search on non-downsampled reconstructed data around the best match macroblock to find a more precise match to use for motion vector coding.
It is a still further object of the invention to provide a processor that performs a hierarchal search motion estimation or a full search motion estimation based, for example, on host commands.
It is a still further object of the invention to provide for a motion estimation processor to determine the best-match of the motion estimation search, with hand-shaking for pipeline control of coprocessors and with determination of the memory addresses used to search the picture.
It is a still further object of the invention to provide for calculation of the motion vector and to send the motion vector data to the Variable Length Encoder for entropy coding.
It is a still further object of the invention to weight best-match motion vectors in order to bias motion vectors as close to the current macroblock as possible.
SUMMARY OF THE INVENTION
These and other objectives of the invention are achieved by the digital video encoder of the invention. The digital video encoder processor system has a video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For encoding bitstreams with temporal compression, that is, IP and IPB bitstreams, the encoder system includes a motion estimation processor (MEPROC) element with a reference memory interface, motion estimation and compensation capability, inverse quantization, inverse discrete cosine transformation, and motion compensation means. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips.
REFERENCES:
patent: 5768537 (1998-06-01), Butter et al.
Boice Charles E.
Curley Lawrence D.
Kaczmarczyk John M.
Ngai Agnes Y.
Stein Charles J.
Britton Howard
International Business Machines - Corporation
McGuireWoods LLP
Steinberg, Esq. William H.
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