Motion estimation architecture for area and power reduction

Details Motion estimation architecture for area and power reduction Motion estimation architecture for area and power reduction

1998-03-23

2000-02-01

Britton, Howard

Television

Image signal processing circuitry specific to television

Motion vector generation

348416, H04N 734

Patent

active

060209348

ABSTRACT:
A method for compensating for reduced picture quality when combining a multi-chip encoding chipset into a single integrated semiconductor IC. The method includes additional functions provided on the single IC to compensate for the negative effects on picture quality produced as a result of rounding 8 bit luminance pixel data to 5 bits, where the luminance data values are supplied as input to the search function. The additional functions are collectively referred to as motion biasing and are applied to influence the choice of a "best match" motion type, which is well known in the art. The biasing is performed by the addition of a weight factor to a total difference result that is calculated by the search function. The biasing is applied only for the purpose of influencing the choice of a reference frame that is not necessarily the frame which produces an optimal motion vector, but rather will result in using fewer bits to encode macroblocks.

REFERENCES:
patent: 4369463 (1983-01-01), Anastassiou
patent: 5608656 (1997-03-01), Purcell

Affiliated with

Also associated with

Rating

Motion estimation architecture for area and power reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Motion estimation architecture for area and power reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Motion estimation architecture for area and power reduction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-941833