Boots – shoes – and leggings
Patent
1997-10-15
1999-05-25
Ngo, Chuong Dinh
Boots, shoes, and leggings
348415, G06F 750, H04N 712
Patent
active
059075007
ABSTRACT:
A motion compensation adder for increasing a motion compensation processing speed is provided in a microprocessor having a multiply-accumulate instruction. A pixel value of a predicted picture which is expressed by an unsigned value is loaded into a register, and the most significant bit is inverted to format-convert the pixel value to a signed value with -128-offset. When hexadecimal constant 0.times.01000000 as a multiplicand, a signed error value as a multiplier and the format-converted pixel value of the predicted picture stored in the most significant byte of the register as an addition value are supplied to a multiply-accumulate instruction having a clipping function, the multiply-accumulate instruction performs the addition of the pixel value of the predicted picture and the error value and the clipping processing needed for the motion compensation adding processing by only one instruction.
REFERENCES:
patent: 5457481 (1995-10-01), Sohn et al.
patent: 5619256 (1997-04-01), Haskell et al.
patent: 5737022 (1998-04-01), Yamaguchi et al.
Kouhei Nadehara et al., "Low-Power Multimedia RISC", IEEE Micro, Dec. 1995, pp. 20-28.
NEC Corporation
Ngo Chuong Dinh
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