Motion compensated de-interlacing in video signal processing

Details Motion compensated de-interlacing in video signal processing Motion compensated de-interlacing in video signal processing

2005-09-27

2005-09-27

Kostak, Victor R. (Department: 2614)

Television

Format conversion

Line doublers type

C348S714000

Reexamination Certificate

active

06950143

ABSTRACT:
A processing circuit for motion compensated de-interlacing of video signals, having a line memory21, a de-interlacing circuit22, a frame memory24, and a cache memory25, further includes a pixel mixer29interposed between the cache memory25and the de-interlacing circuit22.

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