Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-11-03
2002-04-16
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06373458
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a motion circuit which is composed of polycrystalline silicon semiconductor layers and has a logical circuit performing established operations with a normal phase and a reverse phase clock signal, and more specifically, to a motion circuit comprising a shift register such as a transfer gate type shift register, which shifts an entered start signal in time with a normal phase and a reverse phase clock signal.
The present invention also relates to an on-board driver circuit for a liquid crystal display panel employing the motion circuit.
(2) Description of the Prior Art
Driver circuits displaying images on a matrix display panel have been required to perform higher-speed operations as the display panel has a larger screen and higher resolution. To meet the demands, a driver circuit unit is generally made of a high-speed single crystalline silicon LSI and connected to a display panel from outside.
FIG. 25
is a circuit diagram showing the structure of a general driver circuit for a display panel. The diagram shows an external timing circuit
41
, a scanning side driver circuit
42
, an image signal side driver circuit
43
, and a matrix display panel
44
. The scanning side driver circuit
42
mainly consists of a shift register and a buffer. The image signal side driver circuit
43
comprises, when its image signal source is analog, a shift register, a buffer, and an analog switch, and comprises, if the image signal source is digital, a shift register, a latch, and a D/A converter as shown in FIG.
25
. As for circuit operations, the external timing circuit
41
supplies the shift registers contained in the scanning side driver circuit
42
and the image signal side driver circuit
43
with start signals and clock signals. These two driver circuits select pixels on arbitrary positions on the display panel, thereby driving the pixel transistors ON so as to write image signals sequentially. The clock signals supplied from the external timing circuit
41
to the driver circuits
42
and
43
are single phase clock signals from which internal inverters
50
and
51
generate reverse phase clock signals.
On the other hand, it has been suggested that a display unit and a driver circuit should be formed on the same substrate of a display panel by employing polycrystalline silicon thin-film transistors. As shown in
FIG. 26
, the display panel
49
contains a scanning side driver circuit
46
and an image signal side driver circuit
47
, and directly enters the output signals of the external timing circuit
45
. The on-board driver circuit operates basically in the same manner as the driver circuit composed of single crystalline silicon; the driver circuit selects arbitrary pixels on the display unit
48
, thereby driving the pixel registers ON as to write image signals sequentially. However, polycrystalline silicon is inferior to single crystalline silicon in the speed of transmitting clock signals to the driver circuits, so a normal phase and a reverse phase clock signal have to be entered instead of a single phase clock signal.
The reason for this is as follows. In the driver circuits
42
and
43
composed of single crystalline silicon, a delay time caused when single phase clock signals entered from the external timing circuit
41
are logical-reversed in the internal inverters
50
and
51
so as to generate reverse clock signals is so small that the phase difference (hereinafter referred to as skew) between the normal phase and the reverse phase clock signal causes no serious problems. In contrast, the use of polycrystalline silicon causes a longer delay time in the inverters, so that the generation of the normal phase and the reverse phase clock signal from the single clock signal might cause malfunctions of the driver circuit due to the skew between the normal phase and the reverse phase clock signal. In other words, a large skew between the normal phase and the reverse phase clock signal causes a so called fail phenomenon according to which the shift registers cannot latch signals at each stage sent from a previous stage, which prevents signals normally shifted in time from being outputted from the shift registers. As a result, the driver circuit causes malfunctions. To avoid the trouble, conventional driver circuits composed of polycrystalline silicon semiconductor layers are operated with a normal phase and a reverse phase clock signal having a small skew, which are directly supplied from an external timing circuit.
In the on-board driver circuit shown in
FIG. 25
, supplying a normal phase and a reverse phase clock signal from the external circuit
41
requires two clock signal lines for each of the scanning side driver circuit
42
and the image signal side driver circuit
43
, so that a total of four clock signal lines are needed for external connection, which causes troublesome connecting operations.
In the on-board driver circuit composed of polycrystalline silicon semiconductor layers shown in
FIG. 26
, on the other hand, the characteristics of the thin-film transistors are far poorer than a driver circuit composed of single crystalline silicon, so that the power-supply voltage must be set at a higher level than in a MOSFET integrated circuit with single crystalline silicon. Consequently, the on-board driver circuit needs signal level conversion corresponding to the difference in power supply voltage when a signal is entered from an external circuit (MOSFET integrated circuit) composed of single crystalline silicon. For this, a level shifter circuit
100
is provided. However, the level shifter circuit
100
is made of thin-film transistors composed of polycrystalline silicon, so a normal phase and a reverse phase clock signal having no clock skew have a clock skew when passing the level shifter circuit
100
. Thus, the fail phenomenon is caused when two-phase clock signals are entered, the same as when a single phase clock signal is entered, which makes it impossible to secure stable circuit operations of the shift registers.
In order to realize a smaller and thinner liquid crystal display panel, it has been considered to built a timing circuit on the same board as other units; however, it is impossible unless the fail phenomenon due to a clock skew is solved.
These problems are common to all motion circuits which are composed of polycrystalline silicon semiconductor layers and which have shift registers shifting start signals in time with a normal phase and a reverse phase clock signal.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems, the object of the present invention is to provide a motion circuit which reduces the occurrence of the fail phenomenon due to the skew between a normal phase and a reverse phase clock signal for driving shift registers, thereby performing stable circuit operations with no malfunctions.
(1) In order to achieve the object, a first group of inventions comprises a clock skew reduction means for entering a normal phase clock signal and a reverse phase clock signal having a clock skew therebetween and for outputting a normal phase clock signal and a reverse phase clock signal having little clock skew therebetween to the shift register. The specific structure of the clock skew reduction means is realized by one of the following requirements (a)-(d) when a normal phase and reverse phase clock signals are generated from an entered single phase clock signal:(a) latch operations of the first and second latch circuits, (b) optimization of the transistor size of the first and second inverter chain circuits, (c) provision of a delay circuit on the reverse phase clock signal line side, or (d) provision of an inverter for each stage or for several stages of the shift register. As a result, a reduction in the skew between the normal phase and reverse phase clock signals secures stable operations of the shift register. Besides the shift register, the present invention is applicable to all kinds of logical circuits performing established operations b
Adachi Katsumi
Yamakura Makoto
Mengistu Amare
Parkhurst & Wendel LLP
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