Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
1999-11-15
2001-09-25
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S377000, C257S382000, C257S384000
Reexamination Certificate
active
06294797
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the device structure and manufacturing of transistors in the semiconductor fabrication, and more specifically, to a metal oxide semiconductor field effect transistor (MOSFET) and a method for forming the metal oxide semiconductor field effect transistor having an elevated source/drain.
BACKGROUND OF THE INVENTION
From the first invention of integrated circuits at 1960, the number of devices on a chip has grown in an explosive increasing rate. The technologies of the semiconductor industry has been researched continuously for almost four decades. The progress of the semiconductor integrated circuits has step into ULSI (ultra large scale integration) level or even higher level. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. The integrated circuits devices like the transistors, the capacitors, and the connections must be greatly narrowed simultaneously.
The increasing packing density of the integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every device needs to be formed within smaller size without damaging the characteristics and the operations of integrated circuit devices. The demands on high packing density, low heat generation, and low power consumption devices with good reliability and long operation life must be maintained without any degradation in their functions. These achievements are expected to be reached with the five key aspects of the semiconductor manufacturing, including the photography, the etching, the deposition, the ion implantation, and the thermal processing technologies. The continuous increase in the packing density of the integration circuits must be accompanied with a smaller feature size. With the present semiconductor manufacturing technology, the processes with generally a quarter micrometer in size is widely utilized. For making the next generation devices, the technologies focusing mainly on one-tenth micrometer and even nanometer feature sizes are highly required.
Transistors, or more particularly the metal oxide semiconductor field effect transistors (MOSFET), are the most important and frequently employed devices. The MOSFET is widely employed in the integrated circuits with it's high performance. However, with the continuous narrowing of the device size, the sub-micron scale MOS transistors have to face many risky challenges. As the MOS transistors become narrower and thinner accompanying with shorter channels, the problems like the junction punchthrough, the leakage, and the contact resistance cause the reduction in the yield and the reliability of the semiconductor manufacturing processes.
For developing fixture MOSFET devices with a sub-micrometer or even smaller feature size, the ultra shallow junctions are required to suppress the short channel effects encountered with the down scaling sizes. On the other hand, new challenges arise with a narrowed size. The preparation of an extremely shallow source/drain junction is much harder. The conventional ion implantation process is unable to form a shallow junction with high dopant concentration.
In the work proposed by K. Takeuchi et al. (“High performance sub-tenth micron CMOS using advanced boron doping and WSi
2
dual gate process”, in 1995 Symposium on VLSI Technology Digest of Technical Papers), the problem is addressed. The ion implantation is hard to form shallow and high concentration source/drain. The defect-induced anomalous diffusion of boron in the channel region becomes a problem. Local boron depletion near the source/drain junctions will directly enhance short channel effects. A CMOS fabrication method is also disclosed in their work.
In addition, a device degradation problem is found to come from the boron penetration into the thin gate oxide with the formation of a doped polysilicon gate. S. L. Wu (the inventor of the present invention), C. L. Lee, and T. F. Lai submit the problem in their work “Suppression of Boron Penetration into an Ultra-Thin Gate Oxide (≦7nm) by Using a Stacked-Amorphous-Silicon (SAS) Film” (IEDM 93-329 1993 IEEE). The p+polysilicon has been widely used as the gate material of pMOSFET to avoid the short-channel effects. The BF
2
-implant is typically used in forming both the gate and the junction.
However, in the conventional arts in forming the transistors, the F-incorporation will enhance the boron penetration through the thin gate oxide into the silicon substrate. The penetration also results in a large threshold voltage shift. A SAS gate structure is proposed to suppress the F-incorporation-induced boron penetration effect in their work.
SUMMARY OF THE INVENTION
A metal oxide semiconductor field effect transistor (MOSFET) device and a method of forming the metal oxide semiconductor field effect transistor with an elevated source/drain is provided in the present invention. The short channel effects can be suppressed with the elevated junction. An extended ultra-shallow source/drain junction is formed by a plasma immersion process or a low energy implantation. The effects accompanying with the small feature size devices are eliminated by the extended ultra-shallow junction.
The method of the present invention in forming a transistor, more specifically a MOSFET, on a semiconductor substrate includes the following steps. A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the anti-reflection layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region.
An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first dielectric layer is then removed and another doping step is performed to dope the second silicon layer for forming a source/drain junction in the substrate under a region uncovered by the gate region and the undoped spacer structure.
A series of process is then performed to form a metal silicide layer on the gate region and the source/drain junction region. At first, a metal layer is formed over the semiconductor substrate, and a thermal process is then performed to the semiconductor substrate, in order to diffuse and activate dopants in the extended source/drain junction and in the second silicon layer to form the source/drain junction, and also to form a metal silicide layer on the second silicon layer and the first silicon layer. Finally, the unreacted portion of the metal layer is removed.
In the preferred embodiments, a step of thermally growing a second dielectric layer on the substrate is carried out after the doping step for forming an oxynitride layer around the gate region and the gate insulator layer to reduce the dopant penetration or contamination to the gate insulator layer.
The present invention proposed a transistor device on a semiconductor substrate, the transistor includes a stacked gate structure over the semiconductor substrate, a gate insulator layer between the first silicon layer and the semiconductor substrate, a second silicon layer on the semiconductor substrate, a junction region and an extended junction region. The stacked gate structure has a first silicon layer over the semiconductor substrate and an undoped spacer structure on sidewalls of the first silicon layer. The second silicon layer is on the semiconductor substrate at a region uncovered by the stacked gate structure and isolation regions. The junction region is in the semiconductor substrate under the second silicon layer but not under the stacked gate structure. The extended junction region is in the semiconductor substrate under the undoped spacer structure.
In
Texas Instruments - Acer Incorporated
Wojciechowicz Edward
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